Stateflow provides graphical and tabular interfaces for modeling system logic using state machines. In a state machine, you model the system's modes of operation as states and represent the logic for switching between modes using transitions and junctions. You can model the different components in your system as states that execute exclusively or in parallel. Stateflow lets you manage the complexity of your design by organizing state diagram objects, functions, and components hierarchically.
In Stateflow you can represent combinatorial logic graphically with flow charts and in tabular format with truth tables.
Designing logic involves defining conditions to be checked and subsequent actions to be performed. Stateflow enables you to define conditions and actions in C or in MATLAB®. You can manage the data used in conditions and actions from the Simulink® Model Explorer. Before executing your design, Stateflow notifies you of possible state inconsistencies, unused data and events, and invalid transitions.
Stateflow provides an editor and graphical objects for drawing state machines and flow charts. You build a state machine by selecting states, transitions, and junctions from a graphical palette and dragging them into the Stateflow Editor. You can also create functions using flow chart notation, Simulink subsystems, MATLAB, and truth tables. Your Stateflow diagram can be specified as a hybrid of Mealy and Moore machines with extended functionality, a Mealy machine, or a Moore machine.
You can create flow charts by drawing transitions that are connected at junctions and execute based on conditional logic. The Pattern Wizard lets you create commonly used logic flow patterns. Flow charts can be placed in graphical functions for use in many locations in the state diagram and in other state diagrams in the same model. You can use flow charts to design the logic for transitioning between states.
The Stateflow Editor provides edit-time checks to identify illegal object placement and invalid transitions.
State transition tables in Stateflow provide a structured environment for modeling state machines. You build a state machine by adding rows for states, and columns for the transitions between states. State transition tables help you create state machines by providing dropdown menus for state names, automatic completion of finite state machine syntax, and other edit-time checks. Before executing your model, you can run static diagnostic tests to detect syntax errors, incomplete transitions, and unreachable states.
The state transition matrix view generated from state transition tables lets you quickly identify conditions and possible destination states from a particular state.
Truth tables in Stateflow let you model logic that does not require the maintenance of a state over successive runs. You build a truth table by entering conditions to be checked followed by combinations of outcomes for those conditions. Actions can then be entered for different outcome combinations. After building the truth table, you can run static diagnostic checks to identify over-specified and under-specified conditions.
After creating components in Stateflow, you can integrate them with other components to build your state machine algorithm. Stateflow components can contain MATLAB and Simulink functions, custom C code, graphical functions, and truth tables. In your algorithm, you can schedule component and function execution using time-based and condition-based logic.
Each Stateflow component can be developed, executed, and verified independently, enabling multiple users to work on different parts of the algorithm at the same time.
You can reuse a component across diagrams and models by right-clicking it, converting it to an atomic subchart, and placing it in a library. To use the component, you drag it from the library and drop it into your diagram or model. When you update a component in the library, all instances of the component are automatically updated. You can organize components and functions hierarchically to represent your system concisely and accurately.
Reusing States Multiple Times in a Diagram
Create and reuse components in Stateflow for large-scale modeling.
You can model conditional and time-based logic in Stateflow to call Simulink functions and MATLAB functions. Events based on logic modeled in Stateflow can be output to Simulink to activate subsystems that react to a function call or to changes in the control signal.
Stateflow provides event-based and time-based operators (before, after, at, and every) that let you specify state-transition logic based on event counts and elapsed time without using timers and counters.
Schedule Execution of Simulink Subsystems
Use time-based and condition-based logic to schedule Simulink® functions.
You can analyze the behavior of your system by simulating your model. You can run what-if scenarios by restarting the simulation from any saved state and analyzing its reaction to different settings and configurations.
In Stateflow you can visualize system behavior during simulation by using state diagram animation to highlight the active states and transitions in your model.
Stateflow debugging capabilities let you step through the simulation in detail. You can set breakpoints, monitor data values, and step through different functions in your state diagrams. From the Stateflow debugger window, you can control the simulation execution and display the diagram's call stack and execution status.
The Stateflow debugger detects run-time errors, including state inconsistencies, data range violations, and potential infinite loops.
During simulation you can visualize the simulation results by:
Alternatively, you can log diagram and state activity data for post-processing in MATLAB.
By using Stateflow with other Simulink products, you can validate your design against requirements and generate code for implementation on your embedded system.
With Simulink Verification and Validation, you can map requirements directly to Stateflow objects, check for standards compliance, and collect model coverage metrics.
With Simulink Design Verifier, you can detect design errors and generate test vectors for hard-to-find errors using formal methods.