Accelerating Test Bench Creation for Verilog and VHDL Designs Using MATLAB®, Simulink®, and Link for ModelSim®

Using traditional methods, writing the necessary test benches for a digital hardware design is very time consuming and siphons effort away from optimizing the design itself.

In this webinar, to be broadcast live on July 13, 2006, we will demonstrate how engineers designing in Verilog or VHDL can write their test benches in a fraction of the time using MATLAB, Simulink, and Link for ModelSim. In addition, if test benches originally created to validate the executable specification are available, you can reuse them for verification of the design, leading to further time saving and fewer errors.

Pre-registration is required.

  See schedule and registration information

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