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Free ASIC Design Information Kit

Learn how to streamline your ASIC design process with MATLAB and Simulink.

ASIC Design and Verification with MATLAB and Simulink

MathWorks HDL code generation and verification products enable ASIC design engineers to quickly generate synthesizable Verilog and VHDL code for ASIC development. You can accelerate the design and verification of your ASIC projects by using HDL Coder and HDL Verifier.

With HDL Coder and HDL Verifier you can:

  • Perform HDL design iterations in minutes rather than weeks
  • Automatically generate HDL code and Verilog and VHDL test benches for ASIC prototyping and design
  • Verify that your HDL implementation matches your MATLAB and Simulink system specification
  • Create ASIC prototypes of MATLAB and Simulink algorithms on Xilinx® and Altera® FPGAs
  • Generate test vectors to achieve 100% coverage.

Complete the form for access to technical resources that demonstrate how these products help produce high-performance ASIC designs in far less time than with conventional methods.


  • HDL Code Generation for Digital Filters
  • HDL Coder Overview
  • Introduction to HDL Verifier

Recorded Webinars

  • Implementing MATLAB Algorithms In FPGAs and ASICs
  • FPGA and ASIC Verification Made Easy
  • Using HDL Coder and HDL Verifier for FPGA and ASIC Designs
  • Using MATLAB and Simulink for ASIC Prototyping and Verification

User Stories

  • FLIR Accelerates Development of Thermal Imaging FPGA
  • Siglead Shortens Development Time for FPGA and ASIC Signal Processing Systems for Storage Devices
  • Semtech Speeds Development of Digital Receiver FPGAs and ASICs
  • Wolfson Microelectronics Accelerates Audio Hub Design Verification
  • Yokogawa Electric Develops Key Components for Next-Generation Optical Networks with Simulink and Mentor Graphics ModelSim
  • Faraday Accelerates SIP Development and Shrinks NAND Flash Controller ECC Engine Gate Count by 57% with Model-Based Design

Technical Articles

  • Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
  • Converting MATLAB Algorithms into Serialized Designs for HDL Code Generation
  • FPGA-Based Wireless System Design
  • Designing a Sigma-Delta ADC from Behavioral Model to Verilog and VHDL
  • Automatic Hardware Implementation of Digital Filters for an Audio Codec with MediaTek

Data Sheets

  • HDL Verifier
    Verify VHDL and Verilog using HDL simulators and FPGAs
  • Filter Design HDL Coder
    Generate HDL code for fixed-point filters
  • HDL Coder
    Generate HDL code from Simulink models and MATLAB code

Contact Us

Call MathWorks: 508-647-7000