You can design and simulate your algorithm using MATLAB, Simulink, and Stateflow, then generate code for Altera® FPGAs using HDL Coder. In Altera DSP Builder, you can generate HDL code for Altera FPGAs using Altera-specific blocks, and use HDL Coder to generate code from Simulink models containing both native Simulink blocks and Altera-specific blocks. With HDL Verifier, you can verify hardware implementations produced by either HDL Coder or DSP Builder.
Using HDL Coder, you can automatically generate VHDL and Verilog code for Altera FPGAs from MATLAB, Simulink, and Stateflow models. This approach supports a variety of system objects available in products such as Communications System Toolbox and DSP System Toolbox.
With HDL Coder and Altera Quartus® II, you can automatically synthesize your design and program the bitstream on your selected FPGA board. HDL Coder generates a VHDL test bench for functional verification. Additionally, HDL Coder outputs highly traceable code for applications that must adhere to certification standards such as DO-254.
HDL Coder can generate target-specific HDL code with Altera megafunctions. Floating-point megafunctions are a set of parameterized floating-point IP blocks optimized for Altera FPGAs. Mapping to floating-point megafunctions enables you to synthesize your floating-point design without requiring floating-point to fixed-point conversion. This approach offers several advantages:
DSP Builder enables you to create designs optimized for Altera FPGAs in Simulink without requiring that you work directly with HDL code. With DSP Builder Advanced Blockset, you specify top-level design constraints, such as desired clock frequency and number of channels in your Simulink model. DSP Builder then automatically generates pipelined RTL targeted and optimized for your selected FPGA device. Because Advanced Blockset uses time-division multiplexing to optimize logic utilization and automatically inserts pipeline stages and registers to meet design constraints, you can achieve performance on FPGAs similar to hand-optimized HDL code.
DSP Builder incorporates a high-performance, low-latency floating-point tool flow using fused datapath technology. This capability enables the design engineer to build signal processing datapaths that combine floating-point and fixed-point operations.
HDL Coder supports code generation for Simulink models constructed with a combination of blocks from from Altera DSP Builder Advanced Blockset. The DSP Builder Subsystem block in HDL Coder enables you to include models built with Altera DSP Builder Advanced in Simulink. HDL Coder uses Altera DSP Builder to generate code from the subsystem blocks and integrate the complete design into synthesizable HDL code.
This approach enables you to:
With Model-Based Design, design teams can simulate models for complete systems and use C/C++ and HDL code generation from Simulink to target Altera devices. These devices offer a combination of ARM® Cortex® -A9 cores along with the programmable logic of a conventional Altera FPGA.
In this hardware-software workflow, you generate C/C++ with Embedded Coder® for your software model, and can use HDL Coder™ to generate Verilog and VHDL to produce IP cores from your hardware model. Using optimizations provided with the coders, you customize generated code for your target Altera SoC. For example, you can use resource sharing and distributed pipelining from HDL Coder to improve the efficiency of your FPGA implementation. Similarly, you can use configuration options and processor-specific optimizations provided with Embedded Coder to improve MCU and DSP execution performance on ARM Cortex-A9 cores. For NEON™-optimized code for DSP filters, you can use the ARM Cortex-A Ne10 Library Support from DSP System Toolbox.
Using Embedded Coder and HDL Coder support packages for Altera SoC, you integrate generated C/C++ and HDL code into your implementation, use Altera Quartus II for synthesis and place and route, and target your selected SoC.
With HDL Verifier, you can verify code using your MATLAB or Simulink model as a system-level test bench and cosimulating generated code with HDL simulators from Mentor Graphics® or Cadence®. You can perform hardware-in-the-loop verification using your model again as a system-level test bench and executing generated code on Altera FPGA boards. HDL Verifier accepts hand-written HDL or HDL automatically generated by either HDL Coder or DSP Builder.
HDL Coder and HDL Verifier provide an integrated environment for generating, programming, and verifying HDL implementations for FPGAs.