You can design and simulate your algorithm using MATLAB, Simulink, and Stateflow, then generate code for Altera® FPGAs using HDL Coder. In Altera DSP Builder, you can generate HDL code for Altera FPGAs using Altera-specific blocks. With HDL Verifier, you can verify hardware implementations produced by either HDL Coder or DSP Builder. While the system-level test bench runs in Simulink, code generated by these tools executes on an HDL simulator or FPGA board to verify that the code correctly implements the design.
Using HDL Coder, you can automatically generate VHDL and Verilog code for Altera FPGAs from MATLAB, Simulink, and Stateflow models. This approach supports a variety of system objects available in products such as Communications System Toolbox and DSP System Toolbox.
With HDL Coder and Altera Quartus® II, you can automatically synthesize your design and program the bitstream on your selected FPGA board. HDL Coder generates a VHDL test bench for functional verification. Additionally, HDL Coder outputs highly traceable code for applications that must adhere to certification standards such as DO-254.
HDL Coder can generate target-specific HDL code with Altera megafunctions. Floating-point megafunctions are a set of parameterized floating-point IP blocks optimized for Altera devices. Mapping to floating-point megafunctions enables you to synthesize your floating-point design without requiring floating-point to fixed-point conversion. This approach offers several advantages:
With HDL Verifier, you can verify code using your MATLAB or Simulink model as a system-level test bench and cosimulating generated code with HDL simulators from Mentor Graphics® or Cadence®. You can perform hardware-in-the-loop verification using your model again as a system-level test bench and executing generated code on actual FPGA boards. HDL Verifier accepts hand-written HDL or HDL automatically generated by either HDL Coder or DSP Builder.
HDL Coder and HDL Verifier provide an integrated environment for generating, programming, and verifying HDL implementations for FPGAs.
DSP Builder enables you to create designs optimized for Altera FPGAs in Simulink without requiring that you work directly with HDL code. With DSP Builder Advanced Blockset, you specify top-level design constraints, such as desired clock frequency and number of channels in your Simulink model. DSP Builder then automatically generates pipelined RTL targeted and optimized for your selected FPGA device. Because Advanced Blockset uses time-division multiplexing to optimize logic utilization and automatically inserts pipeline stages and registers to meet design constraints, you can achieve performance on FPGAs similar to hand-optimized HDL code.
DSP Builder incorporates a high-performance, low-latency floating-point tool flow using fused datapath technology. This capability enables the design engineer to build signal processing datapaths that combine floating-point and fixed-point operations.