You can design and simulate algorithms using MATLAB, Simulink, and Stateflow, then generate code for Xilinx® FPGAs using HDL Coder. In Xilinx System Generator for DSP, you can generate HDL code for Xilinx FPGAs using Xilinx-specific blocks. Finally, using HDL Coder and System Generator together, you can generate code from models containing both native Simulink blocks and Xilinx-specific blocks.
Using HDL Coder, you can automatically generate VHDL and Verilog code for Xilinx FPGAs from MATLAB, Simulink, and Stateflow models. This approach supports a variety of system objects available in products such as Communications System Toolbox and DSP System Toolbox.
With HDL Coder and Xilinx ISE® Design Suite, you can automatically synthesize your design and program the bitstream on your selected FPGA board. HDL Coder generates a VHDL test bench for functional verification. Additionally, HDL Coder outputs highly traceable code for applications that must adhere to certification standards such as DO-254.
HDL Coder can generate target-specific HDL code with Xilinx LogiCORE IP. The Xilinx Floating-Point Operator core supports a set of floating-point arithmetic functions optimized for synthesis on Xilinx devices. Mapping to an FPGA target-specific floating-point library enables you to synthesize your floating-point design without requiring floating-point to fixed-point conversion. This approach offers several advantages:
With HDL Verifier, you can verify code using your MATLAB or Simulink model as a system-level test bench and cosimulating generated code with HDL simulators from Mentor Graphics® or Cadence®. You can perform hardware-in-the-loop verification using your model again as a system-level test bench and executing generated code on actual FPGA boards.
HDL Coder and HDL Verifier provide an integrated environment for generating, programming, and verifying HDL implementations for FPGAs.
Using System Generator, you can automatically generate HDL code for FPGAs from Simulink models. You create models of algorithms for implementation in FPGAs using high-level components from Xilinx-specific blocksets. Xilinx libraries include blocks for communication, control logic, signal processing, mathematics, and memory.
With your model, you compile the design to an HDL netlist ready to be processed by a synthesis tool and automatically implemented with Xilinx ISE Design Suite. System Generator produces the following:
HDL Coder supports code generation for Simulink models constructed with a combination of blocks from Simulink and Xilinx-specific blocksets from System Generator. The System Generator Subsystem block in HDL Coder enables you to include models built with System Generator in Simulink as subsystems. HDL Coder uses System Generator to generate code from the subsystem blocks and integrates the complete design into synthesizeable HDL.
This approach enables you to: