SERDES simulation can cause problems for circuit simulators. Circuit complexity coupled with high data rates can slow simulations to a crawl, which threatens project delivery times and limits the scope for design exploration.
SERDES design using Simulink® is much faster. Simulink's sophisticated time handling, coupled with its controls design background, mean that circuit loops can be simulated quickly. Impairments such as noise and jitter can be included in the system-level simulation, increasing accuracy. As William Walker of Fujitsu states: "By including circuit-level simulation results in our Simulink models, we can simulate millions of cycles with the accuracy needed to account for noise and other transient effects. Simulink is the only tool fast enough for our jitter-tolerance simulations."
Though cosimulation and links to other EDA tools, system-level SERDES designs can be linked to EDA tools for the next stage of the design process.