Hardware-in-the-Loop (HIL) Simulation for Embedded Systems

• Verification, Validation, and Test Overview
• Early Requirements Validation
• Design Verification
• Embedded Software Test and Verification
• Digital and Analog Hardware Verification
• Hardware-in-the-Loop (HIL) Simulation for Embedded Systems

Hardware-in-the-Loop (HIL) Simulation for Embedded Systems

HIL simulation minimizes costs and risks in embedded system development by enabling you to test your embedded system before deploying it in a production environment. You test your embedded system in real time by connecting it to a simulation of the remaining design. This approach enables you to use the same system-level models throughout the development process, from design to real-time HIL simulation.

Test Embedded Systems with Real-Time System Simulation

HIL simulation begins with a system-level model that includes your embedded system algorithm and its operating environment. You can automatically generate C code and HDL code from the plant and environment models to run on a real-time simulator that delivers inputs and receives outputs from the embedded system as the real system would. As a result, you obtain greater value from the system-level model for testing and verifying the real-time performance of your embedded system.

HIL simulation is especially valuable when:

• The system is not yet built.
• Safety and performance concerns dictate testing the system prior to human involvement.
• You need to minimize expensive downtime for the real system.
• You need to test operation and failure conditions that are difficult to physically replicate.

Verify Algorithm Behavior on FPGAs Using Simulink Cosimulation

FPGA HIL simulation enables you to verify FPGA implementations of algorithms by leveraging a Simulink system model as a virtual test harness. Blocks in your Simulink system model define connections to an FPGA development board running handwritten or automatically generated HDL code. During simulation, signals from the system model are automatically routed to the FPGA, where the algorithm runs, and the signals from the FPGA return to the next Simulink block. Products from Altera, Xilinx, and MathWorks automatically generate the interconnectivity for FPGA HIL simulation.