Advanced HDL Code Generation for FPGAs Using MATLAB and Simulink

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Stephan Van Beek, MathWorks

Learn how to use MathWorks products to produce FPGA implementations of algorithms modeled in MATLAB and Simulink with higher performance and greater efficiency.

This is the second of a three-part series on FPGA design using MATLAB and Simulink. In this webinar, we focus on demonstrating new capabilities in Simulink HDL Coder and other MathWorks products, including the following topics:

  • Identifying critical paths to determine performance bottlenecks
  • Inserting and balancing distributed pipelining to increase achievable operating frequency
  • Choosing block implementations to meet timing and resource constraints
  • Modeling and implementing multirate designs

The webinar also includes demonstrations showing how to verify HDL in designs involving feedback.

About the Presenter:
Stephan van Beek is a Signal Processing and Communications Engineer Application Engineer for MathWorks focused on FPGA implementation. Prior to joining MathWorks, Stephan worked at Anorad Europe BV as a field service engineer on motion control systems. After that he worked at Océ-Netherlands as an application engineer responsible for FPGA tool flows. Stephan studied electrical engineering at the Polytechnic in Eindhoven.

Product Focus

  • HDL Coder
  • HDL Verifier

Recorded: 2 Jun 2010