Design Filters and Verify Filter Designs for FPGAs

Stephan Van Beek, MathWorks

Are you designing filters in MATLAB for implementation on FPGAs?  Learn how to shorten and improve your HDL filter design and verification effort. 

In this webinar we demonstrate how to use MATLAB and your HDL simulator simultaneously for better implementation, debugging, and verification to:

•    explore different filter design techniques and HDL implementation strategies
•    perform subjective analysis in MATLAB while using your HDL simulator
•    prototype hardware from MATLAB (using automatic HDL code generation)
•    use automatic test bench creation to eliminate manual scripting

Find out how engineering teams are reducing verification time by 75-90% and cutting development time in half.

Through demonstrations you will learn about how cosimulation and code generation capabilities plug into your existing design flow. You will see how this eliminates time-consuming and repetitive tasks and improves the quality of debug and verification.

Product Focus

  • Filter Design HDL Coder
  • Signal Processing Toolbox
  • Fixed-Point Designer
  • DSP System Toolbox
  • HDL Verifier

Recorded: 23 Jun 2009