Eliminating Design Errors in Your Algorithm Using Simulink Design Verifier

Nishaat Vasi, MathWorks

Many engineers test their algorithm models in simulation. Through simulation they identify design and requirement errors in their model before generating production code. However, eliminating design errors remains a challenge and extensive testing with 100 percent coverage may still result in a design that contains robustness errors such as overflows and divide-by-zero. Some of these errors may reveal themselves under rare conditions and could be time consuming to debug. They may be induced by certain calibration values and only be found on the HIL bench or in a test vehicle. This presentation illustrates a method for detecting and eliminating such design errors using Simulink Design Verifier.

Product Focus

  • Simulink
  • Stateflow
  • Simulink Design Verifier

Recorded: 13 May 2014