Accelerating the pace of engineering and science

FPGA and ASIC Verification Made Easy

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Sudeepa Prakash, MathWorks

In this webinar, you will learn how you can accelerate your FPGA and ASIC verification, speed your design iterations, and increase confidence in your silicon implementation.

Using HDL Verifier™, you can automate cosimulation between MATLAB® or Simulink® and Mentor Graphics® ModelSim® and Cadence® Incisive® HDL simulators. For faster simulation and to verify actual silicon implementation, you can use FPGA-in-the-loop with Xilinx® and Altera® boards. Using HDL Coder™ you can perform rapid prototyping on FPGAs or implement your HDL design on ASICs and FPGAs directly from MATLAB or Simulink.

Highlights include the following:

• Cosimulation with ModelSim
• FPGA-in-the-loop verification with Xilinx and Altera boards
• Verilog® and VHDL® code generation using HDL Coder
• Programming your HDL code on Xilinx and Altera FPGA boards

About the Presenter: Sudeepa Prakash is product marketing manager for HDL and embedded code generation at MathWorks. Prior to joining MathWorks, she was an embedded software engineer at Johnson Controls Inc. Sudeepa has also worked with scientists at LRDE in India on digital modules for radar systems using HDL code generation. She has a master’s degree in computer science from the University of Wisconsin- Milwaukee and a bachelor’s in electronics and communications from Visvesvaraya Technological University.

Product Focus

  • HDL Verifier
  • HDL Coder
  • Filter Design HDL Coder

Recorded: 27 Sep 2012