Implementing a Wireless Receiver on an FPGA, Part 3: Implementing and Verifying the Design on Target Hardware

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Frank Liu, MathWorks
Idin Motedayen-Aval, MathWorks
Jason Bryan, MathWorks

In the final section of this three-part series, we will implement and verify the design on target hardware by doing the following:

  • Develop an implementation friendly architecture from the behavioral model
  • Convert the floating point model into fixed-point
  • Automatically generate HDL code and integrate the code with target hardware
  • Verify the design using HDL co-simulation and FPGA-in-the-loop on a Xilinx Spartan-6 Evaluation Kit

Product Focus

  • HDL Coder
  • Fixed-Point Designer
  • HDL Verifier

Recorded: 29 Aug 2012