Accelerating the pace of engineering and science

Using HDL Coder and HDL Verifier for FPGA and ASIC Designs

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Stephan van Beek, MathWorks

In this webinar learn how you can leverage our HDL Code Generation and Verification products to accelerate your FPGA design cycle and avoid costly mistakes. Using HDL Coder you can prototype your algorithm on FPGAs or implement it on ASICs and FPGAs directly from Simulink.  With HDL Verifier, you can co-simulate your HDL code with ModelSim and perform FPGA based accelerated simulations.

MathWorks engineers will demonstrate the latest enhancements to HDL Coder, which generates synthesizable Verilog® and VHDL® code from Simulink models, MATLAB code, and Stateflow charts.  

We will discuss the following topics:

  • Simulink system level design
  • Verilog and VHDL code generation using HDL Coder
  • Optimization techniques for efficient FPGA implementation
  • Pipelining and resource sharing
  • Co-simulation with ModelSim
  • Programming your HDL code on FPGA boards
  • FPGA-in-the-Loop verification

About the Presenter: Stephan van Beek is a Signal Processing and Communications Engineer Application Engineer for MathWorks focused on FPGA implementation. Prior to joining MathWorks, Stephan worked at Océ-Netherlands as an application engineer responsible for FPGA tool flows. He has also worked as a field service engineer for motion control systems at Anorad Europe BV. Stephan studied electrical engineering at the Polytechnic in Eindhoven.

Product Focus

  • HDL Coder
  • HDL Verifier

Recorded: 29 May 2012