Eric Cigan, MathWorks
In part 3, we use prototype hardware to determine whether a change in the velocity controller running on the ARM solves the design failure identified in the previous part of the presentation.
In this part, we go into more detail about how HDL Coder is used to generate an IP core targeted to the Zynq SoC devices programmable logic, and show how this workflow provides traceability between Simulink models and generated C and HDL code.
The presentation concludes with a brief discussion of how this workflow supports integration of C and HDL code into production workflows.
This video is part 3 of a three-part series demonstrating how MathWorks product support prototyping of motor controllers on Zynq SoCs.
About the Presenter: Eric Cigan is in MathWorks technical marketing supporting FPGA design workflows. Prior to joining MathWorks, he held technical marketing roles at Mentor Graphics, AccelChip, and MathStar. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology.
Recorded: 17 Mar 2014