From the series: Prototyping Motor Controllers on Zynq SoCs Using MATLAB and Simulink
Eric Cigan, MathWorks
In part 3, we use prototype hardware to determine whether a change in the velocity controller running on the ARM solves the design failure identified in the previous part of the presentation.
In this part, we go into more detail about how HDL Coder is used to generate an IP core targeted to the Zynq SoC devices programmable logic, and show how this workflow provides traceability between Simulink models and generated C and HDL code.
The presentation concludes with a brief discussion of how this workflow supports integration of C and HDL code into production workflows.
About the Presenter: Eric Cigan is in MathWorks technical marketing supporting FPGA design workflows. Prior to joining MathWorks, he held technical marketing roles at Mentor Graphics, AccelChip, and MathStar. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology.
Recorded: 17 Mar 2014
Model-Based Design of a Motor Controller on Xilinx Zynq SoCs
In part 1, we demonstrate the flow from desktop simulation to prototyping for a six-step trapezoidal motor controller.
Enhancing a Zynq Motor Controller to Address Additional Requirements Using Simulation
In part 2, a new requirement for the motor control systems is introduced, causing the initial design to fail dramatically in hardware. Using simulation, we then show how to diagnose the issue, and propose a design change to the velocity controller ex
Verifying Design Changes by Prototyping on the Zynq Intelligent Drives Kit
Part 3: Verifying design changes by prototyping on the Zynq Intelligent Drives Kit In part 3, we use prototype hardware to determine whether a change in the velocity controller running on the ARM solves the design failure identified in the previous p