MATLAB and Simulink Seminars

Best Practices for Mixed-Signal Verification by Generating SystemVerilog DPI-C with MATLAB and Simulink

Start Time End Time
29 Jun 2023, 10:00 AM PDT 29 Jun 2023, 11:00 AM PDT


Mixed Signal Verification continues to be one of the most challenging phases of the chip design process. We will present solutions to accelerate verification by generating DPIC and SystemVerilog components directly from higher level MATLAB and Simulink models. These can be used in the DV environment or for AMS verification with Cadence Virtuoso frameworks. Some of the benefits to using MATLAB and Simulink components are: 

  • Simulating functional behavior of analog/mixed signal components in digital/SoC simulations or with Cadence Spectre® with AMS simulations 
  • Avoiding file-based methods to apply stimulus and check expected results 
  • Automating the process of bringing model changes into verification environments 
  • Speeding up simulations by using DPI-C components to apply stimulus or check results
  • Constructing more intelligent stimulus generators or checkers
  • Creating reference models automatically for training and calibration behavior to test digital and firmware implementations  

In this seminar, we will cover following aspects of the process:  

  • How to generate algorithm reference models, re-use stimulus, and analyze models directly from MATLAB/Simulink 
  • Modeling best practices for code generation
  • Co-simulating Simulink models with circuits running on Cadence Virtuoso Spectre simulator 
  • How to generate DPIC components to be used with Cadence Virtuoso AMS simulations 
  • Learn how leading customers are shifting verification to the system-level to eliminate costly issues early 
  • Hardware implementation: data types, frame vs sample-based, cycle accurate models 
  • Parametrizable stimulus with random constraints capabilities 
  • Integration into UVM  

About the Presenter

Jesson John is the analog mixed-signal segment industry marketing manager at MathWorks. He works with semiconductor, electronics, and communications companies worldwide on improving design and verification workflows for AMS, SerDes, and Signal Integrity systems. Previously, he was a Senior RF/AMS IC Design engineer and Product Development Manager at Maxlinear Inc and Resonant Inc (now Murata) respectively. Jesson has a master’s degree in Electrical and Computer engineering from the University of Florida.

Mark Lin is an advanced application engineer supporting ASIC/FPGA workflows who specializes in digital design verification. Mark was a verification engineer at Broadcom for eight years, where he developed full-chip test environments. He earned a BS degree in electrical engineering from California State University of Los Angeles.

This event is part of a series of related topics. View the full list of events in this series.

Best Practices for Mixed-Signal Verification by Generating SystemVerilog DPI-C with MATLAB and Simulink

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