Best Practices for Mixed-Signal Verification by Generating SystemVerilog DPI-C with MATLAB and Simulink

Mixed Signal Verification continues to be one of the most challenging phases of the chip design process. We will present solutions to accelerate verification by generating DPIC and SystemVerilog components directly from higher level MATLAB and Simulink models. These can be used in the DV environment or for AMS verification with Cadence Virtuoso frameworks. Some of the benefits to using MATLAB and Simulink components are: 

• Simulating functional behavior of analog/mixed signal components in digital/SoC simulations or with Cadence Spectre® with AMS simulations 
• Avoiding file-based methods to apply stimulus and check expected results 
• Automating the process of bringing model changes into verification environments 
• Speeding up simulations by using DPI-C components to apply stimulus or check results
• Constructing more intelligent stimulus generators or checkers
• Creating reference models automatically for training and calibration behavior to test digital and firmware implementations  

In this seminar, we will cover following aspects of the process:  

• How to generate algorithm reference models, re-use stimulus, and analyze models directly from MATLAB/Simulink 
• Modeling best practices for code generation
• Co-simulating Simulink models with circuits running on Cadence Virtuoso Spectre simulator 
• How to generate DPIC components to be used with Cadence Virtuoso AMS simulations 
• Learn how leading customers are shifting verification to the system-level to eliminate costly issues early 
• Hardware implementation: data types, frame vs sample-based, cycle accurate models 
• Parametrizable stimulus with random constraints capabilities 
• Integration into UVM