Improve ASIC and FPGA Verification Productivity by Connecting to MATLAB and Simulink

Date Time
13 Aug 2020
5:30 AM EDT

Overview

Functional verification typically consumes the largest amount of time and resources on ASIC, SoC, and FPGA design projects. Despite this, bugs still make it into silicon at a higher rate than desired. One of the root causes is the communication gap between algorithm design and implementation.

System-level behavioral models in MATLAB and Simulink helps bridge this gap by serving as reusable verification components, which reduces the testbench development efforts. This allows issues to be discovered earlier in design cycle, saving precious time and effort. In addition, rapid behavioral simulations using MathWorks tools enable increased verification coverage.

In this talk, we will look at different approaches for increasing verification efficiency like:

  • Cosimulation of MATLAB and Simulink with EDA simulators
  • SystemVerilog DPI component generation for Universal Verification Methodology (UVM) and reuse of testbenches
  • Hardware-based verification through FPGA-in-the-loop testing

About the Presenter

Nitin Rai is an application engineer at MathWorks India specializing in design and implementation of digital signal processing applications. He works closely with customers across domains to help them adopt MATLAB® and Simulink®. Nitin previously worked for the Indian Space Research Organization as a project engineer for five years and was involved with the design and realization of aerospace mechanisms, integration activities, and checking out operation of the launch vehicles. Nitin hold a master’s degree in digital systems and telecommunication from The Australian National University (ANU), Canberra and a bachelor’s degree in avionics from the Indian Institute of Space Science and Technology (IIST), Kerala.

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