Functional verification typically consumes the largest amount of time and resources on ASIC, SoC, and FPGA design projects. Despite this, bugs still make it into silicon at a higher rate than desired. One of the root causes is the communication gap between algorithm design and implementation.
System-level behavioral models in MATLAB and Simulink helps bridge this gap by serving as reusable verification components, which reduces the testbench development efforts. This allows issues to be discovered earlier in design cycle, saving precious time and effort. In addition, rapid behavioral simulations using MathWorks tools enable increased verification coverage.
In this talk, we will look at different approaches for increasing verification efficiency like:
- Cosimulation of MATLAB and Simulink with EDA simulators
- SystemVerilog DPI component generation for Universal Verification Methodology (UVM) and reuse of testbenches
- Hardware-based verification through FPGA-in-the-loop testing