Decode 5G NR Wireless Signals on an FPGA

Date Time
8 Sep 2020
5:30 AM EDT
8 Sep 2020
9:00 AM EDT
8 Sep 2020
2:00 PM EDT

Overview

Learn how to transition 3GPP 5G New Radio (NR) and other wireless communications algorithms to FPGA-based implementation by building a connected workflow and using hardware-proven IP and reference applications.

Highlights

  • Workflow and methodology
  • How to use 5G IP blocks
  • Overview of the 5G NR Cell Search reference application
  • Targeting Xilinx Zynq-based hardware
  • Generating SystemVerilog verification components
  • Example customer projects

Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand. 

About the Presenter

As a senior applications engineer, Jeff Miller focuses on supporting customers for adopting HDL code generation and 5G/LTE technology. Customer projects have included HDL designs for high performance FFT, FIR, Matrix Mathematics, Encryption, Custom Floating Point, and LTE receivers. Prior to joining MathWorks, Jeff worked at Applied Signal Technology doing Signal Intelligence, and at Morphics Technology doing commercial wireless communications. Jeff has a Master’s of Electrical Engineering from Georgia Tech and a Master’s of Education from the University of Arizona.

Jack Erickson is responsible for product marketing and product management for the HDL product family at MathWorks. Prior to joining MathWorks, he spent over 20 years at Cadence Design Systems, Inc., as an applications engineer and in product marketing for simulation, RTL synthesis, and high-level synthesis. He has a BSEE from Tufts University and an MBA from Worcester Polytechnic Institute.

Product Focus

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