Early FPGA/SoC Design Verification with Simulink and the
Vivado Simulator from AMD-Xilinx
|Start Time||End Time|
|27 Oct 2022, 5:30 AM EDT||27 Oct 2022, 6:30 AM EDT|
|27 Oct 2022, 9:00 AM EDT||27 Oct 2022, 10:00 AM EDT|
|27 Oct 2022, 2:00 PM EDT||27 Oct 2022, 3:00 PM EDT|
Versal ACAP is a software-programmable, heterogeneous compute platform that combines processing cores, programmable logic, and AI engines. Versal devices can be used to accelerate machine learning inference and advanced signal processing workloads such as beamforming, FFTs, and filters.
Versal designs include legacy RTL code for the programmable logic (PL) along with functions that have been newly implemented for the high-performance AI engine array. Since designs for Versal are partitioned across the different Versal engines, it is important to functionally verify all new design content in the context of the complete design.
An approach that enables fast, functional simulation of a hybrid system is to simulate using MATLAB and Simulink in combination with Vitis Model Composer.
In this webinar, engineers from AMD-Xilinx and MathWorks will demonstrate techniques for early functional verification of designs that use both the PL and the AI engine array functions.
- Performing fast functional cosimulation of a design that uses both PL and AI engine implementation
- Performing cycle-approximate cosimulation of imported HDL code (using Vivado Simulator)
- Using MATLAB and Simulink testbenches to verify implementation on AMD-Xilinx development boards with FPGA-in-the-Loop testing
- Generating SystemVerilog testbench components automatically for use with Vivado verification environments
Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.
About the Presenters
Rob Graessle is a staff product development engineer with AMD/Xilinx, focusing on Vitis Model Composer. He has more than 10 years of experience working in and for the DoD on radar and software-defined radio applications. His passion is taking projects from requirements to simulation to prototype, then experiencing the thrill of seeing designs come to life. Rob earned BS and MS degrees in Computational Science & Engineering from Miami University.
Eric Cigan is a principal product marketing manager at MathWorks for ASIC and FPGA design and verification. Prior to joining MathWorks, he held technical marketing roles at Mentor Graphics, MathStar, and AccelChip. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology. In his spare time, Eric curates a wide-ranging, ever-growing collection of development boards from AMD/Xilinx, Avnet, and other sources.
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