A 2018 study revealed that 84% of FPGA design projects – including some safety-critical designs - suffered from non-trivial bugs escaping into production, with 10% having four or more bugs released into production.
In this webinar, MathWorks engineers will demonstrate a series of techniques that FPGA design teams in industry are using today to verify correct performance of FPGA designs using MATLAB and Simulink.
- Use MATLAB and Simulink test benches to verify that RTL implementations conform to specification models, then use these same test benches to verify implementation on with hardware testing on FPGA and SoC boards.
- Debug FPGA implementations from MATLAB and Simulink by inserting probes and triggers within designs to capture internal signals during hardware testing and analyzing results in MATLAB.
- Use test harnesses in Simulink to achieve Simulink test benches with high levels of functional coverage, then generate SystemVerilog or UVM test bench components automatically for use in production verification environments.
MathWorks engineers will demonstrate these techniques using example designs.
Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.
About the Presenters
Mark Lin in an advance application engineer supporting ASIC/FPGA workflows who specializes in digital design verification. Mark was a verification engineer at Broadcom for eight years, where he developed full-chip test environments. He earned a BS degree in electrical engineering from California State University of Los Angeles.
Eric Cigan is the principal product marketing manager for ASIC and FPGA verification at MathWorks. Prior to joining MathWorks, he held technical marketing roles at MathStar, AccelChip, and Mentor Graphics. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology.