Optimize FPGA and ASIC Speed and Area Using HDL Coder
|Start Time||End Time|
|28 Jul 2022, 5:30 AM EDT||28 Jul 2022, 6:30 AM EDT|
|28 Jul 2022, 9:00 AM EDT||28 Jul 2022, 10:00 AM EDT|
|28 Jul 2022, 2:00 PM EDT||28 Jul 2022, 3:00 PM EDT|
Learn how to use HDL Coder optimization and design techniques to meet your target-specific speed and area goals. HDL Coder offers techniques that span from automatic to fully-controlled, and all of them allow for rapid exploration of implementation options. This webinar will explain these options and their associated benefits and tradeoffs, including verification considerations, and will discuss techniques specific to FPGA and ASIC targeting. All of these techniques will be demonstrated using the pulse detection design from the HDL Self-Guided Tutorial.
- Workflow options from rapid estimation to running full synthesis and implementation
- Optimizing for speed
- Latency vs throughput vs clock frequency
- Pipelining techniques
- Vector processing
- Multiplier mapping
- Optimizing for area
- Resource sharing
- RAM mapping
- Loop streaming of vector operations
Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.
About the Presenter
Eric Cigan is a principal product marketing manager at MathWorks for ASIC and FPGA verification. Prior to joining MathWorks, he held technical marketing roles at Mentor Graphics, MathStar, and AccelChip. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology. In his spare time, Eric curates a wide-ranging, ever-growing collection of FPGA development boards from manufacturers around the world.
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