By Mike Woodward, MathWorks and Tim Reeves, MathWorks
SERDES data processing rates vary widely. At the low end, SERDES systems are used in car rear-view camera systems, where the data rate is usually less than 1 Gbps. At the high end, they are used in high-bandwidth Internet optical routers, where the data rate is 10 Gbps or more.
SERDES designers use SPICE simulators, which are accurate, but very computationally intensive. As a result, simulating SERDES devices running at data rates above 10 Gbps using a SPICE simulator is extremely time-consuming, limiting opportunities for design exploration and increasing the cost of design errors.
To speed up simulation, designers are turning to a much faster approach: top-down design. Top-down design uses a behavioral model to rapidly simulate system performance. Designers can quickly evaluate design alternatives, and use SPICE simulation to test only the best performing design.
In this article, we demonstrate top-down design of a SERDES model with Simulink® and show how the model can be used to reduce simulation times. The model used in this example can be downloaded from the Simulink Mixed-Signal Library.
Some communications systems send data serially across channels—for example, Internet data sent along fiber-optic cables and car rear-view camera data sent along twisted-pair wires. Because electronic systems process data in parallel, these systems need a way to convert from serial to parallel, and vice versa. This is the job of the serializer-deserializer (SERDES) system (Figure 1).
Channels distort the signals sent along them by, for example, distorting the pulse shape or adding variable delays. A SERDES device receiving a signal across a channel must be able to reconstruct that signal, a process requiring both analog and digital processing. A SERDES is therefore a mixed-signal device.
To build a representative system, we used a 10 Gbps data rate and incorporated data transmission and reception, including jitter, channel modeling, crosstalk, clock and data recovery, 8b/10b encoding/decoding, and equalization (Figure 2). Our goal is to get the model to simulate a microsecond’s worth of data in under 10 minutes on a quad-core laptop computer.
Because we need our system to work with a specific backplane, our first step is to model the backplane. We used measured backplane data, which is in the form of 16-channel, single-ended S-parameters. This is a large data set, and it considerably slows down the simulations.
To speed up the simulations, we build a more compact model. From the backplane data we extract two-port data for the forward and crosstalk channels, and use the rational fitting function from RF Toolbox™ to fit a Laplace domain model to this data subset. This compact model is still an accurate representation of our measured data, but it runs considerably faster than a model that uses the full S-parameter data.
We choose a random data source for both the forward and crosstalk channels, and encode both channels with 8b/10b coding. We introduce jitter into our transmitter as part of the transmitter’s feedforward equalization filter, and add RMS and peak-to-peak jitter reporting to the model.
Because the channel will distort the signal, causing intersymbol interference (ISI), we use filtering to help preserve the signal's integrity. Our filter design is based on the assumption that the filter plus the channel model is a linear time-invariant system. We split the filtering into two parts, placing filtering both before and after the channel. The postchannel filtering is part of the equalization process. The prechannel filtering is pre-emphasis filtering using a three-tap FIR filter. Pre-emphasis filtering suppresses ISI at the center of the data symbol.
The equalizer consists of two parts. The first is a set of standard analog bandpass filters that provide coarse equalization. The second (the mixed-signal equalizer) provides finer equalization to minimize the effects of ISI, and uses both internal and external feedback. The external feedback comes from the recovered clock block, and the internal feedback comes from the feedback equalizer filter (Figure 3). Both the feed-forward equalizer (FFE) and the feedback equalizer (FBE) use FIR filters, with parameters calculated using the DFE block from Communications System Toolbox™.
The feedback loops involved in equalizer design slow simulation of SPICE models because SPICE solvers can take a great deal of time to converge. Because Simulink takes a behavioral-level approach, Simulink is much faster than SPICE simulators at simulating feedback. Depending on the model, the speedup in simulation time can be tenfold or more.
In SERDES systems, clock recovery typically uses a bang-bang PLL architecture because it is easier to implement in silicon. This architecture, again, uses feedback (Figure 4).
We base our voltage-controlled oscillator (VCO) on an actual VCO device, taking data from a published device data sheet to simulate component performance. Because VCO phase noise strongly affects the performance of the CDR as a whole, we model the phase noise performance of a real device. We choose coefficients for the lead/lag filter to give sufficient bandwidth and a fast locking time.
In the clock and data recovery (CDR) subsystem, analog and digital elements work together. The D latch is a digital device, but the other components are analog. In Simulink, analog and digital components can be connected just as they would be in an actual device. The underlying simulation engine takes care of the necessary simulation changes.
Most of our SERDES model components output analog signals. To speed up analog simulation, Simulink uses a variable-step solver, which dynamically adjusts the time steps used during simulation in response to block outputs. When block outputs change rapidly, Simulink chooses a shorter time step, but when outputs change slowly, Simulink chooses a longer time step. In this way, Simulink maintains fast simulation without sacrificing accuracy.
Simulink sends the recovered data through an 8b/10b decoder and compares it to the original transmitted data in the Compare Signals block. The differences between the transmitted and recovered signal are insignificant (Figure 5).
The model has a range of other plots available—for example, we can compare the received data with the recovered clock and data, and examine the eye diagram at the output of the analog equalizer (Figure 6).
Because of the fast execution speed, we can interactively investigate the properties of the system while the simulation is running. We can vary model parameters and investigate their effect on the system as a whole.
The SERDES model includes a dialog box for controlling noise power. By varying the noise power while the simulation is running, we can discover the operational limits of our design. We find that our design can recover the clock and data at noise levels up to about 15 dBm, but beyond that point, the eye diagram starts to close, and we observe differences between the transmitted and received signals.
We can also evaluate our system’s ability to recover from transmit jitter. We run the simulation and gradually increase the jitter introduced in the forward channel transmitter. At about 17ps of RMS jitter, our receiver cannot correct for jitter, the eye diagram starts to close, and errors creep into the data output by the receiver. Again, we perform this test interactively in minutes.
Finally, we simulate 1x10-6 s worth of data passing through the system. The simulation takes just 600 seconds on a quad-core laptop computer. We not only met our simulation goal—we exceeded it.
These tests would be almost impossible to perform interactively in a SPICE model. With our Simulink model, we get results within minutes.
Simulink models run substantially faster than SPICE models, enabling engineers to swiftly evaluate design alternatives under a range of operating conditions. Because of the high computational demands of high-data-rate SERDES simulation, Simulink is one of the few design environments that enable engineers to thoroughly simulate SERDES systems and still meet tight project deadlines.
Published 2012 - 92059v00