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Keeping Everyone in the Loop: Designing a Better Analog-to-Digital Converter

By Luis Hernandez and Susana Paton, Universidad Carlos III de Madrid, and Dietmar Sträussnigg, Infineon Technologies

As mixed-signal designers, we face continual challenges as process technology improves. We are often asked to produce designs that use lower voltages, take up smaller chip areas, and need less computing power. Sometimes existing architectures can be expanded to meet new requirements, but if they can’t, we need to create something new. At Infineon and Universidad Carlos III de Madrid (UC3M), we’ve been working together on developing new mixed-signal designs for over 10 years.

Technology changes created a unique set of problems for a sigma-delta analog-to-digital converter (ADC) project at Infineon. For ADCs targeted at communication markets, the company wanted to increase converter bandwidth to 20 MHz, reduce power consumption, and use 65 nm process technologies. For the same market, we had previously designed a novel, continuous-time multibit sigma-delta architecture using a flash quantizer. At the new smaller geometry the voltages are lower, giving very low voltages between the resistors in the resistor ladder and making flash difficult to implement. In addition, our flash quantizers consumed much of our chip area and a good deal of the power budget. In short, we needed a new design.

Creating a new device involves multiple design iterations. To accelerate development, we chose a system-level design approach. System-level design is much faster than circuit-level design, and it enables us to simulate many different designs in the time it would take to complete just one circuit-level simulation. System-level design also helps us organize our project better. UC3M is based in Madrid, Spain, and the Infineon team is in Villach, Austria. By working in one system-level environment, our geographically separated teams can develop different parts of the system separately and then demonstrate that the components work together as a single system.

A New Design Concept

A colleague at Infineon who was using time-domain modulation for another project suggested we investigate time encoding with a pulse width modulator (PWM) (Figure 1). This architecture had not been tried before for ADCs, but it offered us a design that did not include flash quantizers, instead using PWM on the oscillating binary signal to quantize the signal. To produce a new device based on this architecture, we set up joint projects between UC3M and Infineon to develop a new, time-encoding sigma-delta with a PWM. UC3M focused on system-level design and Infineon on circuit-level design.

Figure 1. The time-encoding architecture.

The Design Process

In Madrid, our first step was to calculate parameters for our analog loops. We used Richard Schreier’s Delta Sigma Toolbox and a MATLAB® based loop design library that we have built up over several years of working with Infineon. Our design library includes design applications that we built using the MATLAB GUIDE tool. These applications enable us to visualize system performance, for example, using Bode plots. Our analysis tools enabled us to enter broad requirements (for example, the SNR, bandwidth, and clocking frequency) and see how different designs behaved at the highest design level, helping us determine the order of the sigma-delta we need to build (Figure 2).

Figure 2. MATLAB applications used to examine different architectures.

The next stage was to build system-level models in Simulink®. Although MATLAB can do linear analysis of loops, to simulate loops we need Simulink. Simulink enables us to rapidly simulate loops, making it a great choice for fast mixed-signal system simulation.

Using our own extensive library of mixed-signal intellectual property (IP) we quickly tried out different topologies. Once we had a workable design, we added impairments including jitter, finite amplifier bandwidth, mismatches in capacitors, mismatches in DACs, and thermal noise. The goal was to make our system-level simulations as realistic as possible.

For this project, we built an asynchronous PWM as a coarse quantizer to replace the flash quantizer from our previous design work. This change affected the dynamics of the loops in the system, and we had to adjust parameters and make design modifications as a result. In turn, the new architecture meant we had to develop new design tools in MATLAB.

To test our design, we ran MATLAB scripts to vary the Simulink model parameters. Some of these scripts were controlled by a GUI that we used to set up the details of the parameters we wanted to vary and to collect and display the results. Parameter sweeps involve running a large number of simulations, so speed of simulation is important for us to get the results in a timely manner.

At Infineon in Villach, we worked mostly on the digital design elements. We initially considered several different architectural approaches to reduce quantization noise introduced by digital filtering, and the one that gave the best results was the PWM architecture suggested by our colleague. MASH architectures aren’t new, but applying them to PWMs was. The problem was that we needed precise time resolution, which meant clocking the modulators at a high frequency. With physical clocks there is always a residual timing error. With MASH architectures, however, it’s possible to compensate for this sampling error. The idea was to estimate the error with a digital filter estimating the noise transfer function (NTF) of the modulator. We subtracted the estimated error from our signal, resulting in a performance gain of several dB. In Villach, we also used MATLAB and Simulink for our design work.

Obviously, the analog and digital parts of the system must work together, and we needed to ensure that the design work done in Madrid would integrate with the design work done in Villach, and vice versa. This project was part of an ongoing relationship spanning multiple projects over multiple years, so we needed a sustainable way of working together over the longer term. Relying on physical meetings to bring everything together is very expensive and time-consuming, so we evolved a way of working together remotely. We held biweekly conference calls in which we shared results, and held annual workshops when we met for a week or so. Because both teams use MATLAB and Simulink, we were able to share models and results very easily, even though the two teams were located in different countries.

In reality, of course, the boundary between the analog and digital parts of a system is often blurred—the analog team will work on part of the digital system and vice versa. For example, in Villach we looked at how the analog design from Madrid affected the digital part of the system. We also brought the analog and digital parts of the design together to study how the ADC as a whole performed. The ADC itself was part of a larger device built at Infineon, and we modeled how all the component systems, including the ADC, affected the system-level behavior of the device as a whole.

Once we had a system-level model that met our requirements, we moved to circuit-level implementation. We built VHDL® models in Cadence® tools that mimicked the behavior of our system-level models. We replaced each VHDL component with a circuit model until we had an entire design at the circuit level.

Test Results

We taped out a prototype chip using a 65nm CMOS process (Figure 3).

Figure 3. The time-encoded ADC test chip.

We tested the chip in the lab, injecting a clock signal at 2.5 GHz, and received the digital data via a dedicated high-speed interface. Figure 4a shows the measured power spectral density of the digital data when an input tone is applied. The spectra reveal the presence of the PWM oscillator carrier together with the input signal and quantization noise.

Figure 4b shows our measured signal-to-noise ratio and signal-to-noise distortion ratio plotted against the input voltage, indicating a 63 dB dynamic range. Power measurements showed our ADC consumed 7 mW from a 1.0 V supply—comfortably within our requirements.

Figure 4a. Measurement results for power spectral density. Figure 4b. Measurement results for signal-to-noise ratio.

The most remarkable benefit of this novel architecture is the small area consumed by the core—only 0.8 mm2. This small area is an important factor in a multichannel communication SoC where many converters are aligned.

The results from our test chip indicated that we had achieved our goals for the project.

This collaborative project pushed the boundaries of design, which meant investigating many different possible designs and design parameters. Because we needed to investigate and evaluate alternative designs very quickly, the speed of simulation offered by system-level design was a very important factor in making this project work.

We have submitted several patents and published several academic papers on the basic design ideas we used. We’re currently working on a number of other joint mixed-signal projects using the same system-level approach.

Published 2013 - 92086v00


  • Enrique Prefasi, Susana Paton, Luis Hernandez, Richard Gaggl, Andreas Wiesbauer, Joerg Hauptmann, “A 0.08mm 2 7mW time-encoding oversampling converter with 10 bits and 20MHz BW in 65nm CMOS”, Proc. ESSCIRC, 2010
  • Dietmar Sträussnigg, Andreas Wiesbauer, Luis Hernandez, Daniel Mark, “Sampling error reduction in PWM-MASH converters”, US Patent 2009/0109075