By Kiran Kintali and Yongfeng Gu, MathWorks
This paper describes how HDL Coder™ can be used with Altera® DSP Builder in an integrated FPGA workflow. It illustrates this approach using a model that performs FIR filtering and integrates two subsystems, one implemented with blocks from the DSP Builder Advanced Blockset and the other with native Simulink® blocks. The paper shows how HDL Coder can generate HDL code for the complete model design. This capability enables designers to reuse existing DSP Builder models when using HDL Coder to create new designs, or to incorporate target-optimized Altera IP blocks created within Simulink models for use with HDL Coder.