MATLAB Examples

Fully Parallel Systolic FIR Filter Implementation

Implement a 25-tap lowpass FIR filter by using the docid:dsp_ref.bvi0_ng-1 block.

The model filters new data samples at every cycle.


Open the Model

Open the model. Inspect the block parameters. DSP resource sharing and validIn port are disabled.

Run the Model and Inspect Results

Run the model. Observe the input and output signals in the generated plots.

From the model toolbar, open the Logic Analyzer.

Note the pattern of the validOut signal.

Generate HDL Code

To generate HDL code from the Discrete FIR Filter HDL Optimized block, right-click the block and select Create Subsystem from Selection. Then right-click the subsystem and select HDL Code > Generate HDL Code for Subsystem.