Build an LTE compliant OFDM Modulator and Detector for implementation with HDL Coder™, and use LTE System Toolbox™ to verify the HDL implementation model.
Optimize the QPSK transmitter modeled in the QPSK Transmitter and Receiver example for HDL code generation and hardware implementation.
HDL code generation support for the Viterbi Decoder block. It shows how to check, generate, and verify the HDL code you generate from a fixed-point Viterbi Decoder model. This example also
Optimize the QPSK receiver modeled in QPSK Transmitter and Receiver example for HDL code generation and hardware implementation. The HDL-optimized model shows a QPSK receiver that
A hardware friendly model that receives beacon frames in an 802.11 wireless local area network (WLAN) as described in [ 1 ]. For more information refer to the IEEE 802.11 WLAN - Beacon Frame
HDL support is provided for Gamma correction in Vision HDL Toolbox™. This example demonstrates the functionality of the pixel-stream Gamma Corrector block and compares the results with
Use the Vision HDL Toolbox Histogram library block to implement histogram equalization.
When designing video processing algorithms, an important concern is the quality of the incoming video stream. Real-life video systems, like surveillance cameras or camcorders, produce
Demonstrates how to detect and highlight object edges in a video stream. The functionality of the pixel-stream Sobel Edge Detector and Video Alignment blocks is verified by comparing the
Implement a front-end module of an image processing design. This front-end module removes noise and sharpens the image to provide a better initial condition for the subsequent processing.
This error message generally occurs when you have Simulink™ blocks performing floating-point operations inside a feedback loop. These blocks have a latency. HDL Coder™ is unable to
Mark signals as test points in your Simulink™ model and, after HDL code generation, debug the signals at the top level using the generated model or a test bench.
This issue occurs when your Simulink™ model has a significantly large difference in sample rates or uses certain block implementations or optimizations that result in different
Most applications that you target the HDL code for might not require such a large rate differential. In that case, it is recommended that you use a single-rate model. In this example, you can
To model your design at the data rate and selectively increase the sample rate of blocks for which HDL Coder™ is unable to allocate delays, use local oversampling. These blocks then operate at
HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. Native floating-point operators have a latency. When you generate HDL code, the code
Use blocks inside a For Each Subsystem in your Simulink™ model, and then generate HDL code.
Check whether a subsystem or model is compatible for HDL code generation by using the HDL compatibility checker. The HDL compatibility checker examines the specified system for
Utilize RAM resources in your FPGA design using HDL Coder™.
Instantiate multiple top-level synchronous clock input ports in HDL Coder.
Use HDL Coder™ to check, generate and verify HDL for a fixed-point CORDIC model implementing sin and cos trigonometric functions using the MATLAB Function Block.
Effectively use the MATLAB Function block to model commonly used hardware algorithms using HDL Coder™. An HDL design patterns library is used to show the features of MATLAB Coder supported
Use the State Control block to generate hardware-friendly HDL code using HDL Coder.
Use distributed pipelining to optimize a design for speed in HDL Coder.
Balance delays in specific parts of a design, without balancing delays on the entire design.
How HDL Coder can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either
Apply clock rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage. For more information on how to use clock-rate
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see the
How HDL Coder™ manages the execution of operations in the context of clock rate pipelining. By default, if resource sharing is applied in a region of the design operating at the fastest base
Demonstrates how to generate HDL code for a programmable FIR filter. You can program the filter to a desired response by loading the coefficients into internal registers using the host
Demonstrates how to generate HDL code for a discrete FIR filter with multiple input data streams.
The FFT and IFFT HDL Optimized blocks and system objects support simulation and HDL code generation for many applications. They provide two architectures optimized for different use
To reduce the number of multipliers in the HDL implementation of a multichannel filter and surrounding logic, use the StreamingFactor HDL Coder™ optimization.
To reduce the number of multipliers in the HDL implementation of a multifilter design, use the SharingFactor HDL Coder™ optimization.
Combine operations replace several operations with one equivalent operation. Examples of this optimization technique include replacement of a Sin block and a Cos block by a Sincos block.
Constant folding removes redundant operations in your design by evaluating constant subexpressions in advance. This optimization technique identifies Simulink® blocks in your model
Dead code elimination removes a part of the HDL code that is not accessed or is unreachable because of modeling constructs.
Generate a cosimulation model in of HDL Coder and integrate the generated HDL code into an HDL Verifier™ workflow. Automation of cosimulation model generation enables seamless
Use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
Use Xilinx® System Generator for DSP with HDL Coder™.
Use the Altera® DSP Builder Advanced Blockset with HDL Coder™.