This error message generally occurs when you have Simulink™ blocks performing floating-point operations inside a feedback loop. These blocks have a latency. HDL Coder™ is unable to
Mark signals as test points in your Simulink™ model and, after HDL code generation, debug the signals at the top level using the generated model or a test bench.
This issue occurs when your Simulink™ model has a significantly large difference in sample rates or uses certain block implementations or optimizations that result in different
Most applications that you target the HDL code for might not require such a large rate differential. In that case, it is recommended that you use a single-rate model. In this example, you can
To model your design at the data rate and selectively increase the sample rate of blocks for which HDL Coder™ is unable to allocate delays, use local oversampling. These blocks then operate at
HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. Native floating-point operators have a latency. When you generate HDL code, the code
Use blocks inside a For Each Subsystem in your Simulink™ model, and then generate HDL code.
Check whether a subsystem or model is compatible for HDL code generation by using the HDL compatibility checker. The HDL compatibility checker examines the specified system for