This page describes parameters in the Clock Settings section of the HDL Code Generation > Global Settings pane of the Configuration Parameters dialog box. Using these parameters, you can specify the reset name, whether to use a synchronous or asynchronous reset, and whether the reset is asserted active-high or active-low.
Specify whether to use asynchronous or synchronous reset logic when generating HDL
code for registers. It is recommended that you specify the Reset
type as Synchronous when you use a
Xilinx® device and Asynchronous when you use an
Altera® device.
Default:
Asynchronous
AsynchronousUse asynchronous reset logic. This reset logic samples the reset independent of the clock signal.
The following process block, generated by a Unit Delay block, illustrates the use of asynchronous resets. When the reset signal is asserted, the process block performs a reset, without checking for a clock event.
Unit_Delay1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Unit_Delay1_out1 <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
Unit_Delay1_out1 <= signed(x_in);
END IF;
END IF;
END PROCESS Unit_Delay1_process;
SynchronousUse synchronous reset logic. This reset logic samples the reset with respect to the clock signal.
The following process block, generated by a Unit Delay block, checks for a clock event, the rising edge, before performing a reset:
Unit_Delay1_process : PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF reset = '1' THEN
Unit_Delay1_out1 <= (OTHERS => '0');
ELSIF clk_enable = '1' THEN
Unit_Delay1_out1 <= signed(x_in);
END IF;
END IF;
END PROCESS Unit_Delay1_process;
Property:
ResetType |
| Type: character vector |
Value:
'async' | 'sync'
|
Default:
'async' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
For example, you can specify sync as the
ResetType when you generate HDL code for the
symmetric_fir subsystem inside the
sfir_fixed model using either of these methods.
Pass the property as an argument to the
makehdl function.
makehdl('sfir_fixed/symmetric_fir', ... 'ResetType','async')
When you use hdlset_param, you can set the
parameter on the model and then generate HDL code using
makehdl.
hdlset_param('sfir_fixed','ResetType','async') makehdl('sfir_fixed/symmetric_fir')
Specify whether the asserted or active level of the reset input signal is active-high or active-low.
Default:
Active-high
Active-highSpecify that the asserted level of reset input signal is
active-high. For example, the following code fragment checks whether
reset is active high before populating the
delay_pipeline
register:
Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
.
.
.
Active-lowSpecify that the asserted level of reset input signal is
active-low. For example, the following code fragment checks whether
reset is active low before populating the
delay_pipeline
register:
Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
.
.
.
If you input a logic high value to the Reset input port,
to reset the registers in your design, set Reset asserted
level to Active-high. if you input a
logic low value to the Reset input port, to reset the
registers in your design, set Reset asserted level to
Active-low.
Property:
ResetAssertedLevel |
| Type: character vector |
Value:
'active-high' | 'active-low'
|
Default:
'active-high' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
For example, you can specify this property while generating HDL code for the
symmetric_fir subsystem inside the
sfir_fixed model using either of these methods.
Use hdlset_param to set the parameter on the
model. Then generate HDL code using
makehdl.
hdlset_param('sfir_fixed','ResetAssertedLevel','active-high') makehdl('sfir_fixed/symmetric_fir')
Pass the property as an argument to the
makehdl function.
makehdl('sfir_fixed/symmetric_fir','ResetAssertedLevel','active-high')
Enter the name for the reset input port in generated HDL code.
Default:
reset
Enter a character vector for the reset input port name in generated HDL code.
For example, if you override the default with 'chip_reset'
for the generating system myfilter, the generated entity
declaration might look as follows:
ENTITY myfilter IS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
chip_reset : IN std_logic;
myfilter_in : IN std_logic_vector (15 DOWNTO 0);
myfilter_out : OUT std_logic_vector (15 DOWNTO 0);
);
END myfilter;
If you specify a VHDL® or Verilog® reserved word, the code generator appends a reserved word postfix
string to form a valid VHDL or Verilog identifier. For example, if you specify the reserved word
signal, the resulting name string would be
signal_rsvd.
If you specify active-high for Reset asserted level, the reset input signal is asserted active-high. To reset the registers in the entity, the input value to the Reset input port must be high. If you specify active-low for Reset asserted level, the reset input signal is asserted active-low. To reset the registers in the entity, the input value to the Reset input port must be low.
Property:
ResetInputPort |
| Type: character vector |
| Value: A valid identifier in the target language |
Default:
'reset' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
For example, you can specify sync as the
ResetType when you generate HDL code for the
symmetric_fir subsystem inside the
sfir_fixed model using either of these methods.
Pass the property as an argument to the
makehdl function.
makehdl('sfir_fixed/symmetric_fir', ... 'ResetInputPort','rstx')
When you use hdlset_param, you can set the
parameter on the model and then generate HDL code using
makehdl.
hdlset_param('sfir_fixed','ResetInputPort','rstx') makehdl('sfir_fixed/symmetric_fir')