N-Channel metal oxide semiconductor field effect transistor using either Shichman-Hodges equation or surface-potential-based model
Simscape / Electrical / Semiconductors & Converters

The N-Channel MOSFET block provides two main modeling variants:
Based on threshold voltage — Uses the Shichman-Hodges equation to represent the device. This modeling approach, based on threshold voltage, has the benefits of simple parameterization and simple current-voltage expressions. However, these models have difficulty in accurately capturing transitions across the threshold voltage and lack some important effects, such as velocity saturation. For details, see Threshold-Based Model.
This variant provides four ways of parameterizing an N-Channel MOSFET:
By specifying parameters from a datasheet.
By specifying equation parameters directly.
By a 2-D lookup table approximation to the I-V (current-voltage) curve. For details, see Representation by 2-D Lookup Table.
By a 3-D lookup table approximation to the I-V (current-voltage) curve that includes temperature data. For details, see Representation by 3-D Lookup Table.
Based on surface potential — Uses the surface-potential equation to represent the device. This modeling approach provides a greater level of model fidelity than the simple square-law (threshold-voltage-based) models can provide. The trade-off is that there are more parameters that require extraction. For details, see Surface-Potential-Based Model.
Together with the thermal port variants (see Thermal Port), the block therefore provides you with four choices. To select the desired variant, right-click the block in your model. From the context menu, select Simscape > Block choices, and then one of the following options:
Threshold-based — Basic model, which represents the device using the Shichman-Hodges equation (based on threshold voltage) and does not simulate thermal effects. This is the default.
Threshold-based with thermal — Model based on threshold voltage and with exposed thermal port.
Surface-potential-based — Model based on surface potential. This model does not simulate thermal effects.
Surface-potential-based with thermal — Thermal variant of the model based on surface potential.
The threshold-based variant of the block uses the Shichman and Hodges equations [1] for an insulated-gate field-effect transistor to represent an N-Channel MOSFET.
The drain-source current, IDS, depends on the region of operation:
In the off region (VGS < Vth), the drain-source current is:
In the linear region (0 < VDS < VGS –Vth), the drain-source current is:
In the saturated region (0 < VGS –Vth < VDS), the drain-source current is:
In the preceding equations:
K is the transistor gain.
VDS is the positive drain-source voltage.
VGS is the gate-source voltage.
Vth is the threshold voltage. For the four terminal parameterization, Vth is obtained using these equations:
| VBS Range | Vth Equation |
|---|---|
λ is the channel modulation.
The block models junction capacitances either by fixed capacitance values, or by tabulated values as a function of the drain-source voltage. In either case, you can either directly specify the gate-source and gate-drain junction capacitance values, or let the block derive them from the input and reverse transfer capacitance values. Therefore, the Parameterization options for charge model on the Capacitance tab are:
Specify fixed input, reverse transfer and output capacitance
— Provide fixed parameter values from datasheet and let the block convert the input and
reverse transfer capacitance values to junction capacitance values, as described below. This
is the default method.
Specify fixed gate-source, gate-drain and drain-source
capacitance — Provide fixed values for junction capacitance parameters
directly.
Specify tabulated input, reverse transfer and output
capacitance — Provide tabulated capacitance and drain-source voltage
values based on datasheet plots. The block converts the input and reverse transfer capacitance
values to junction capacitance values, as described below.
Specify tabulated gate-source, gate-drain and drain-source
capacitance — Provide tabulated values for junction capacitances and
drain-source voltage.
Use one of the tabulated capacitance options (Specify tabulated input, reverse
transfer and output capacitance or Specify tabulated gate-source,
gate-drain and drain-source capacitance) when the datasheet provides a plot of
junction capacitances as a function of drain-source voltage. Using tabulated capacitance values
gives more accurate dynamic characteristics and avoids the need for interactive tuning of
parameters to fit the dynamics.
If you use the Specify fixed gate-source, gate-drain and drain-source
capacitance or Specify tabulated gate-source, gate-drain and
drain-source capacitance option, the Capacitance tab lets
you specify the Gate-drain junction capacitance, Gate-source
junction capacitance, and Drain-source junction capacitance
parameter values (fixed or tabulated) directly. Otherwise, the block derives them from the
Input capacitance, Ciss, Reverse transfer capacitance,
Crss, and Output capacitance, Coss parameter values. These two
parameterization methods are related as follows:
CGD = Crss
CGS = Ciss – Crss
CDS = Coss – Crss
For the four terminals parameterization, the Input capacitance, Ciss, Reverse transfer capacitance, Crss, and Output capacitance, Coss are obtained using these equations:
CGD = Crss
CGS + CGB = Ciss – Crss
CDB = Coss – Crss
A simplified Meyer's capacitance model is used to describe the gate-source capacitance, CGS, the gate-bulk capacitance, CGB, and the gate-drain capacitance, CGD. These figures show how the gate-bulk and gate-source capacitances change instantaneously, while the

Gate-bulk and gate-source capacitance change instantaneously.

The two fixed capacitance options (Specify fixed input, reverse transfer and
output capacitance or Specify fixed gate-source, gate-drain and
drain-source capacitance) let you model gate junction capacitance as a fixed
gate-source capacitance CGS and either a fixed or a
nonlinear gate-drain capacitance CGD. If you select
the Gate-drain charge function is nonlinear option for the
Gate-drain charge-voltage linearity parameter, then the gate-drain charge
relationship is defined by the piecewise-linear function shown in the following figure.

For instructions on how to map a time response to device capacitance values, see the N-Channel IGBT block reference page. However, this mapping is only approximate because the Miller voltage typically varies more from the threshold voltage than in the case for the IGBT.
Note
Because this block implementation includes a charge model, you must model the impedance of the circuit driving the gate to obtain representative turn-on and turn-off dynamics. Therefore, if you are simplifying the gate drive circuit by representing it as a controlled voltage source, you must include a suitable series resistor between the voltage source and the gate.
For the lookup table representation of the detailed block variant, you provide tabulated values for drain-source currents as a function of gate-source voltage and drain-source voltage. The main advantage of using this option is simulation speed. It also lets you parameterize the device from either measured data or from data obtained from another simulation environment.
This figure shows the implementation of the 2-D lookup table option when you set
Ids-Vds parameterization to Provide negative and positive Vds
data:

This figure shows the implementation of the 2-D lookup table option when you set
Ids-Vds parameterization to Provide positive Vds data
only:

For the four terminal MOSFET, the surface potential and body factor values are calculated based on the nearest threshold voltage as shown in this picture:

For the temperature-dependent lookup table representation of the detailed block variant, you provide tabulated values for drain-source currents as a function of gate-source voltage, drain-source voltage, and temperature.
The surface-potential-based variant of the block provides a greater level of model fidelity than the simple square-law (threshold-voltage-based) model. The surface-potential-based block variant includes the following effects:
Fully nonlinear capacitance model (including the nonlinear Miller capacitance)
Charge conservation inside the model, so you can use the model for charge sensitive simulations
Velocity saturation and channel-length modulation
The intrinsic body diode
Reverse recovery in the body diode model
Temperature scaling of physical parameters
For the thermal variant, dynamic self-heating (that is, you can simulate the effect of self-heating on the electrical characteristics of the device)
This model is a minimal version of the world-standard PSP model (see https://briefs.techconnect.org/papers/introduction-to-psp-mosfet-model/), including only certain effects from the PSP model in order to strike a balance between model fidelity and complexity. For details of the physical background to the phenomena included in this model, see [2].
The basis of the model is Poisson equation:
where:
ψ is the electrostatic potential.
q is the magnitude of the electronic charge.
NA is the density of acceptors in the substrate.
ɛSi is the dielectric permittivity of the semiconductor material (for example, silicon).
ϕB is the difference between the intrinsic Fermi level and the Fermi level in the bulk silicon.
VCB is the quasi-Fermi potential of the surface layer referenced to the bulk.
ϕT is the thermal voltage.
kB is Boltzmann’s constant.
T is temperature.
Poisson equation is used to derive the surface-potential equation:
where:
VGB is the applied gate-body voltage.
VFB is the flatband voltage.
ψs is the surface potential.
γ is the body factor,
Cox is the capacitance per unit area.
The block uses an explicit approximation to the surface-potential equation, to avoid the need for numerical solution to this implicit equation.
Once the surface potential is known, the drain current ID is given by
where:
W is the device width.
L is the channel length.
μ0 is the low-field mobility.
θsat is the velocity saturation.
Δψ is the difference in the surface potential between the drain and the source.
Qinv0 and QinvL are the inversion charge densities at the source and drain, respectively.
is the average inversion charge density across the channel.
Gmob is the mobility reduction factor. For more information, see the Surface roughness scattering factor parameter description in the Main (Surface-Potential-Based Variant) section.
GΔL is the channel-length modulation.
where:
α is the channel-length modulation factor.
VDB is the drain-body voltage.
VDB,eff is the drain-body voltage clipped to a maximum value corresponding to velocity saturation or pinch-off (whichever occurs first).
Vp is the channel-length modulation voltage.
The block computes the inversion charge densities directly from the surface potential.
The block also computes the nonlinear capacitances from the surface potential. Source and drain charge contributions are assigned via a bias-dependent Ward-Dutton charge-partitioning scheme, as described in [3]. These charges are computed explicitly, so this model is charge-conserving. The capacitive currents are computed by taking the time derivatives of the relevant charges. In practice, the charges within the simulation are normalized to the oxide capacitance and computed in units of volts.
The MOSFET gain, β, is given by
The threshold voltage for a short-circuited source-bulk connection is approximately given by
where:
2ϕB is the surface potential at strong inversion.
The overall three and four terminal models consist of an intrinsic MOSFET defined by the surface-potential formulation, a body diode, series resistances, and fixed overlap capacitances, as shown in the schematics.


The block models the body diode either as an ideal, exponential diode or as a tabulated diode.
When you set Model body diode to
Exponential, the junction and diffusion capacitances are:
where:
Idio is the current through the diode.
Is is the reverse saturation current.
VDB is the drain-body voltage.
n is the ideality factor.
ϕT is the thermal voltage.
Cj is the junction capacitance of the diode.
Cj0 is the zero-bias junction capacitance.
Vbi is the built-in voltage.
Cdiff is the diffusion capacitance of the diode.
τ is the transit time.
The capacitances are defined through an explicit calculation of charges, which are then differentiated to give the capacitive expressions above. The block computes the capacitive diode currents as time derivatives of the relevant charges, similar to the computation in the surface-potential-based MOSFET model.
To model a tabulated diode, set the Model body diode parameter to
Tabulated I-V curve. This figure shows the implementation of the
tabulated diode option:

When choosing this parameterization, you must provide the data for the forward bias only.
The block implements the diode using a smooth interpolation option. If the diode exceeds the provided tabulated data range, the block uses a linear extrapolation technique at the last voltage-current data point.
Note
The tabulated diode does not model the reverse breakdown.
The default behavior is that dependence on temperature is not modeled, and the device is
simulated at the temperature for which you provide block parameters. To model the dependence on
temperature during simulation, select Model temperature dependence
for the Parameterization parameter on the Temperature
Dependence tab.
Threshold-Based Model
For threshold-based variant, you can include modeling the dependence of the transistor static behavior on temperature during simulation. Temperature dependence of the junction capacitances is not modeled, this being a much smaller effect.
When including temperature dependence, the transistor defining equations remain the same. The gain, K, and the threshold voltage, Vth, become a function of temperature according to the following equations:
Vths = Vth1 + α (Ts – Tm1)
where:
Tm1 is the temperature at which the transistor parameters are specified, as defined by the Measurement temperature parameter value.
Ts is the simulation temperature.
KTm1 is the transistor gain at the measurement temperature.
KTs is the transistor gain at the simulation temperature. This is the transistor gain value used in the MOSFET equations when temperature dependence is modeled.
Vth1 is the threshold voltage at the measurement temperature.
Vths is the threshold voltage at the simulation temperature. This is the threshold voltage value used in the MOSFET equations when temperature dependence is modeled.
BEX is the mobility temperature exponent. A typical value of BEX is -1.5.
α is the gate threshold voltage temperature coefficient, dVth/dT.
For the four terminals parameterization, Vth is obtained using these equations:
| VBS Range | Vth Equation |
|---|---|
Where:
is the surface potential and .
Eg(0) is the extrapolated zero degree
band-gap, which is equal to 1.16
eV for silicon.
VBS is the bulk-source voltage.
For most MOSFETS, you can use the default value of -1.5 for
BEX. Some datasheets quote the value for α, but most
typically they provide the temperature dependence for drain-source on resistance,
RDS(on). Depending on the block parameterization
method, you have two ways of specifying α:
If you parameterize the block from a datasheet, you have to provide RDS(on) at a second measurement temperature. The block then calculates the value for α based on this data.
If you parameterize by specifying equation parameters, you have to provide the value for α directly.
If you have more data comprising drain current as a function of gate-source voltage for more than one temperature, then you can also use Simulink® Design Optimization™ software to help tune the values for α and BEX.
Surface-Potential-Based Model
The surface-potential-based model includes temperature effects on the capacitance characteristics, as well as modeling the dependence of the transistor static behavior on temperature during simulation.
The Measurement temperature parameter on the Main tab specifies temperature Tm1 at which the other device parameters have been extracted. The Temperature Dependence tab provides the simulation temperature, Ts, and the temperature-scaling coefficients for the other device parameters. For more information, see Temperature Dependence (Surface-Potential-Based Variant).
The block has an optional thermal port, hidden by default. To expose the thermal port, right-click the block in your model, and select the appropriate block variant:
For a model based on threshold voltage and with exposed thermal port, select Simscape > Block choices > Threshold-based with thermal.
For a thermal variant of the model based on surface potential, select Simscape > Block choices > Surface-potential-based with thermal.
This action displays the thermal port H on the block icon, and exposes the Thermal Port parameters.
Use the thermal port to simulate the effects of generated heat and device temperature. For more information on using thermal ports and on the Thermal Port parameters, see Simulating Thermal Effects in Semiconductors.
When modeling temperature dependence for the threshold-based block variant, consider the following:
The block does not account for temperature-dependent effects on the junction capacitances.
When you specify RDS(on) at a second measurement temperature, it must be quoted for the same working point (that is, the same drain current and gate-source voltage) as for the other RDS(on) value. Inconsistent values for RDS(on) at the higher temperature will result in unphysical values for α and unrepresentative simulation results. Typically RDS(on) increases by a factor of about 1.5 for a hundred degree increase in temperature.
You may need to tune the values of BEX and threshold voltage, Vth, to replicate the IDS–VGS relationship (if available) for a given device. Increasing Vth moves the IDS-–VGS plots to the right. The value of BEX affects whether the IDS–VGS curves for different temperatures cross each other, or not, for the ranges of VDS and VGS considered. Therefore, an inappropriate value can result in the different temperature curves appearing to be reordered. Quoting RDS(on) values for higher currents, preferably close to the current at which it will operate in your circuit, will reduce sensitivity to the precise value of BEX.
[1] Shichman, H. and D. A. Hodges. “Modeling and simulation of insulated-gate field-effect transistor switching circuits.” IEEE J. Solid State Circuits. SC-3, 1968.
[2] Van Langevelde, R., A. J. Scholten, and D. B .M. Klaassen. "Physical Background of MOS Model 11. Level 1101." Nat.Lab. Unclassified Report 2003/00239. April 2003.
[3] Oh, S-Y., D. E. Ward, and R. W. Dutton. “Transient analysis of MOS transistors.” IEEE J. Solid State Circuits. SC-15, pp. 636-643, 1980.