Use the clocking options to achieve the CPU clock rate specified on the board. The default clocking values run the CPU clock (CLKIN) at its maximum frequency. The parameters use the external oscillator frequency on the board (OSCCLK) that is recommended by the processor vendor.
For F2837xD and F2838xD dual-core processor, the clock settings are available only when you select the CPU1 option in the Build options > Select CPU parameter. When you select CPU2 option in the Build options > Select CPU parameter, set the CPU clock with the value available in the Achievable SYSCLKOUT in MHz parameter for the CPU1 model.
You can get feedback on the closest achievable SYSCLKOUT value with the specified oscillator clock frequency by selecting the Auto set PLL based on OSCCLK and CPU clock check box. Alternatively, you can manually specify the PLL value for the SYSCLKOUT value calculation.
Change the clocking values if:
You want to change the CPU frequency.
The external oscillator frequency differs from the value recommended by the manufacturer.
To determine the CPU frequency (CLKIN), use the following equation:
CLKIN = (OSCCLK × PLLCR) / (DIVSEL or CLKINDIV)
Where,
CLKIN is the frequency at which the CPU operates, also known as the CPU clock.
OSCCLK is the frequency of the oscillator.
PLLCR is the PLL control register value.
CLKINDIV is the clock in the divider.
DIVSEL is the divider select.
The availability of the DIVSEL or CLKINDIV parameters changes depending on the processor that you select. If neither parameter is available, use the following equation:
CLKIN = (OSCCLK × PLLCR) / 2
You can set the following parameters for clocking on CPU1:
Specify the desired CPU clock frequency (CLKIN). This value is taken automatically for Achievable SYSCLKOUT in MHz = (OSCCLK×PLLCR)/DIVSEL.
Use the internal zero pin oscillator on the CPU. This parameter is enabled by default.
Oscillator frequency used in the processor.
PLL values in PLLCR, DIVSEL, and Achievable SYSCLKOUT in MHz are automatically calculated based on the CPU clock entered on the board.
Specify the system PLL multiplier. You can specify a value in this parameter if Auto set PLL based on OSCCLK and CPU clock is not selected. The PLL multiplier is a 9 bit field with 7 bits of the SYSPLLMULT register comprising of the integer portion and the remaining 2 bits for the fractional portion. You can enter a value in the range between 0 to 127.75 with multiples of 0.25 for fractional portion of the value.
If you select the Auto set PLL based on OSCCLK and CPU clock check box, the auto calculated clock divider value achieves the specified CPU Clock value based on the Oscillator clock frequency. Otherwise, you can select a value for Clock divider (SYSDIVSEL).
The auto calculated feedback value that matches the Desired CPU clock in MHz value, based on the values of OSCCLK, PLLCR, and DIVSEL.
The value using which LSPCLK is scaled. This value is based on SYSCLKOUT.
The value is calculated based on LSPCLK Prescaler.
You can set the following parameters for clocking on CPU2:
Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Achievable SYSCLKOUT in MHz = (OSCCLK*PLLCR)/DIVSEL (auto calculated).
Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Low-Speed Peripheral Clock Prescaler (LSPCLK) specified in CPU1.
The value is calculated based on LSPCLK Prescaler.