Target FPGA with Custom Bitstream

Create Algorithm

Design Guidelines

Create FPGA algorithm in Simulink, following recommended guidelines and limitations. As you develop your new FPGA algorithm in Simulink®, consider the requirements for this workflow.

  • You can use this workflow only when you configure the USRP™ hardware as a single channel receiver only.

  • Output from your targeted subsystem must consist of two 16-bit signed signals to match the output of the existing digital down converter in the FPGA.

  • Multiple input ports must all operate at the same rate as each other. Multiple output ports must also all operate at the same rate as each other.

  • Use scalar mode for HDL Code generation.

The following sections offer suggestions for working within these requirements:

Output Signals

Output from your targeted subsystem must consist of two 16-bit signed signals to match the output of the existing digital down converter (DDC) in the FPGA. If you need to convert signals, for example, you might create a subsystem that converts the output to 16-bit complex integers.

Scalar Mode

Your system should operate in scalar mode for HDL Code generation. You can convert frame-based input signals to scalar by using the Unbuffer block. You can then convert the output back to frame signals using the Buffer block. Within this boundary of Unbuffer and Buffer blocks, the system operates in scalar mode, which is necessary for HDL Code generation.

Set Tool Path

Set up your system environment for to access Xilinx® ISE from MATLAB® with the function hdlsetuptoolpath. This function adds the necessary folders to the MATLAB search path using the Xilinx installation folder as its argument. For example: 

sdrsetup('ToolName', 'Xilinx ISE','ToolPath', 'C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\ise.exe');
Found and setup Communications Toolbox™ Support Package for USRP Radio.

This example assumes that the Xilinx ISE design suite is installed at C:\Xilinx\13.1\ISE_DS\ISE.

Create FPGA Files with HDL Workflow Advisor

  1. Select the subsystem for HDL code generation. This is the subsystem that models the algorithm.

  2. Launch HDL Workflow Advisor by selecting Code > HDL Code > HDL Workflow Advisor.

  3. Set Target (HDL Workflow Advisor step 1).

    At step 1.1, Set Target Device and Synthesis Tool, select the following:

    • For Target workflow: Customization for the USRP Device

    • For Target platform, select one of the following:

      • USRP N210 Board Rev 4.0

      • USRP N210 Board Rev 2.0

  4. Prepare Model for HDL Code Generation (HDL Workflow Advisor step 2).

    Run steps 2.1 through 2.5 to make sure your model is compatible with FPGA targeting.

    Note

    At step 2.5, Check USRP Compatibility, the software checks that the algorithm does not violate any limitations; see Create Algorithm.

  5. HDL Code Generation (HDL Workflow Advisor step 3).

    1. At step 3.1.2, Advanced Options, note the following settings but do not change them — they have been pre-set based on the FPGA Targeting workflow:

      • Reset type: Synchronous

      • Reset asserted level: Active-high

      • Clock inputs: Single

      • Oversampling: 1

      Setting these HDL options generates code that is compatible with the original Ettus ResearchTM USRP FPGA code.

    2. At step 3.2, Generate RTL Code and Testbench, select Generate RTL Code.

  6. Generate FPGA Implementation (HDL Workflow Advisor step 4).

    The USRP Source File Folder is already populated with the path to the USRP FPGA root directory. The relevant USRP FPGA code was downloaded during the installation from Ettus ResearchTM UHD™ Mirror site.

  7. Click Run This Task.

    The HDL Workflow Advisor creates a new Xilinx ISE project and adds the following:

    • All the necessary files from the FPGA repository

    • The generated HDL files for the selected subsystem and algorithm

    If no errors are found during FPGA project generation and syntax checking, the FPGA programming file generation process starts. You can view this process in an external command shell and monitor its progress. When the process is finished, a message in the command window prompts you to close the window.

For additional instructions on using the HDL Workflow Advisor, see the HDL Coder™ documentation.

Burn Custom FPGA File

You can burn the generated FPGA binary using sdruload, specifying the generated FPGA binary usrp_n210_r4_fpga_mw.bin (or usrp_n210_r2_fpga_mw.bin) from a project location such as hdl_prj\usrp_prj. For the firmware image, use the original firmware (usrp_n210_fw_bin) as no changes are made to firmware during FPGA targeting.

Verify FPGA Implementation

To verify your FPGA implementation, first create a new targeted model based on your original model.

  1. Copy your original model to a new model. This new model will be the retargeted model.

  2. Remove the top-level subsystem that you specified during targeting. This subsystem is now programmed onto the FPGA.

  3. If you earlier created a subsystem to create the two 16-bit signed signals required by the FPGA DDC, now put in place a method to reconvert your signals to match the expected output for your model (for example, a subsystem similar to the one you designed to create the signals).

  4. Run simulation. The model now produces real-time data from your algorithm output.

Communications Toolbox Support Package for USRP Radio Documentation

Support