Supported EDA Tools and Hardware

Software

Xilinx Vivado and ISE

Use this support package with these recommended versions:

Xilinx^® Vivado^® 2020.1
Xilinx ISE 14.7
- Xilinx ISE is not supported for FPGA data capture or MATLAB^® AXI master.
- Xilinx ISE is required for FPGA boards in the Spartan^®-6, Virtex^®-4, Virtex-5, and Virtex-6 families.

For tool setup instructions, see Set Up FPGA Design Software Tools.

Board Connections

JTAG Connection

You can run FPGA-in-the-loop, FPGA data capture, or MATLAB AXI master over a JTAG cable to your board. However, each feature requires exclusive use of the JTAG cable, so you cannot run more than one feature at the same time. To allow other tools access to the JTAG cable, such as programming the FPGA, and Xilinx ChipScope, you must discontinue the JTAG connection in MATLAB. To release the JTAG cable:

FPGA-in-the-loop — Close the Simulink^® model, or call the release method of the System object™.
FPGA data capture — Close the FPGA Data Capture app, release the System object, or close the Simulink model.
MATLAB AXI master — Call the release method of the object.

For Xilinx boards, the JTAG clock frequency is 33 or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.

Required Hardware	Required Software
Digilent^® download cable. If your board has an onboard Digilent USB-JTAG module, use a USB cable. If your board has a standard Xilinx 14 pin JTAG connector, you can obtain an HS2 or HS3 cable from Digilent.	For Windows^® operating systems: Xilinx Vivado executable directory must be on system path. For Linux^® operating systems: Digilent Adept2
FTDI USB-JTAG cable Supported for boards with onboard FT4232H, FT232H, or FT2232H devices implementing USB-to JTAG	Supported for Windows operating systems. Note FTDI USB JTAG support is only available for MATLAB as AXI Master and for FPGA Data Capture.

Note

When simulating your FPGA design through Digilent JTAG cable with Simulink or MATLAB, you cannot use any debugging software that requires access to the JTAG; for example, Vivado Logic Analyzer.

Ethernet Connection

You can run FPGA-in-the-loop over an Ethernet connection.

Required Hardware	Supported Interfaces	Required Software
Gigabit Ethernet card Cross-over Ethernet cable FPGA board with supported Ethernet connection	Gigabit Ethernet — GMII Gigabit Ethernet — RGMII Gigabit Ethernet — SGMII Ethernet — MII Ethernet — RMII Note RMII is supported with Vivado versions older than 2019.2.	There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication. Note Ethernet connection to Virtex-7 VC707 not supported for Vivado versions older than 2013.4.

PCI Express

FPGA-in-the-loop over a PCI Express^® connection is supported only for 64-bit Windows operating systems.

Board	Required Software
Kintex^®-7 KC705 Evaluation Kit Virtex -7 VC707 Evaluation Kit Xilinx Virtex-7 VC709 Evaluation Board Virtex UltraScale+™ FPGA VCU118 Evaluation Kit	Vivado 2017.4 or newer.

Documentation