Hardware I/O Devices

Model the connection between the IO devices on your board and your FPGA logic

Use these blocks to create models that simulate the connection between your SoC design and these IO devices.

Blocks

HDMI RxConvert video stream to YCbCr 4:2:2 pixel stream
HDMI TxConvert YCbCr 4:2:2 pixel stream to video frame
AD9361 RxConnect hardware logic to AD9361-based Zynq receiver
AD9361 TxConnect hardware logic to AD9361-based Zynq transmitter
Zynq and FMCOMMS2/3/4 Receiver ConfigurationConnect hardware logic to FMCOMMS Zynq radio receiver hardware
Zynq and FMCOMMS2/3/4 Transmitter ConfigurationConnect hardware logic to FMCOMMS Zynq radio transmitter hardware
ADAU1761 CodecConnect hardware logic to ADAU1761 signals on hardware board
RF Data ConverterProvide RF data path interface to hardware logic
ADC To VectorConvert concatenated 16-bit ADC input samples to vector outputs
Vector To DACConvert vector inputs to concatenated 16-bit DAC output samples

Featured Examples

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design

Design a data path for a Xilinx® RFSoC device by using SoC Blockset®. You will design and simulate a system that generates a sinusoidal tone from an FPGA and transmit the tone across multiple RF channels by using the RF Data Converter (RFDC) block. The system will then receive the data back into the FPGA by using the RFDC block and visualizes the received tone for one channel at a time by using an embedded processor.

Open Example
Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 2 Deployment

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 2 Deployment

Implement and verify a design on Xilinx® RFSoC device using SoC Blockset®. You will deploy a system on Xilinx RFSoC Evaluation kits that generates a sinusoidal tone from an FPGA, transmits it across multiple RF channels and receives it back into the device to complete the loopback. For modeling and simulation of the system, see the Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design example.

Open Example
5G NR MIB Recovery Using Xilinx RFSoC Device

5G NR MIB Recovery Using Xilinx RFSoC Device

Simulate and deploy a 5G NR MIB Recovery algorithm in Simulink® using an SoC Blockset® implementation targeted on the Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can recover, demodulate a primary synchronization signal (PSS) and secondary synchronization signal (SSS) and decodes MIB report from the 5G NR waveforms and simulate the Cell Search control algorithm sequence running on a processor while interacting with the Cell Search hardware algorithm. In simulation, you can fine tune and verify the controller in the processor and hardware algorithm in the FPGA at a system level before implementing them on the hardware.

Open Example
OFDM Transmit and Receive Using Xilinx RFSoC Device

OFDM Transmit and Receive Using Xilinx RFSoC Device

Simulate and deploy an orthogonal frequency division multiplexing (OFDM) transmit and receive algorithm in Simulink® using an SoC Blockset® implementation targeted on a Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can integrate HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples into the SoC Blockset implementation.

Open Example
Vertical Video Flipping Using External Memory

Vertical Video Flipping Using External Memory

Design an application to flip an incoming video stream vertically. You will use external memory to store a video frame to accomplish this task. You can use this technique for designing and implementing other vision applications requiring access to the external memory.

Contrast Limited Adaptive Histogram Equalization with External Memory

Contrast Limited Adaptive Histogram Equalization with External Memory

Implement the contrast-limited adaptive histogram equalization (CLAHE) algorithm for FPGA, including an external memory interface.

SoC Blockset Support Package for Xilinx Devices Documentation

Support