RF Data Converter

Provide RF data path interface to hardware logic

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  • Library:

  • SoC Blockset Support Package for Xilinx Devices / SDR / RFDataConverter

  • RF Data Converter block

Description

The RF Data Converter block provides an RF data path interface to the hardware logic.

The block accepts 16-bit samples packed into N x 16 bits through dacxData ports and outputs a vector of N samples through dacx ports. The block accepts a vector of N samples through adcx ports and outputs 16-bit samples packed into N x 16 bits through adcxData ports based on the N value. N is the number of samples per clock cycle, and the possible values of x range from 1 to m, where m is the maximum number of analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) available on the selected hardware board. The block supports a maximum of 16 ADC and 16 DAC data paths connecting to the hardware logic.

In generation, the SoC Builder tool maps the block parameters to the RF Data Converter IP on the hardware.

The block supports Gen 1, Gen 2, and Gen 3 Zynq® UltraScale+™ RFSoC devices. For a full list of supported devices, see Supported Third-Party Tools and Hardware. For specific Zynq UltraScale+ RFSoC device information, see Zynq UltraScale+ RFSoC Product Information from the Xilinx® website.

Ports

Input

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ADC input data, specified as a column vector.

x indicates the number of adc ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adc ports. For example, if RF interface is set to ADC & DAC 2x2 RF Interface, the block has ports adc1 and adc2, that is, one input port per ADC channel interface.

Valid values for this port are based on the Digital interface parameter value.

  • If you set the Digital interface parameter to Real, specify this value as an N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    Use this option to specify real-valued data. For example, consider N equal to 2 and data containing two real values D0 and D1. In this case, specify this port value as a vector of the form [D0 D1].

  • If you set the Digital interface parameter to I/Q, specify this value as a 2N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    Use this option to specify complex-valued data. For example, consider N equal to 2 and data containing two complex values with real parts I0 and I1 and imaginary parts Q0 and Q1, respectively. In this case, specify this port value as a vector of the form [I0 Q0 I1 Q1].

Data Types: int16 | uint16

DAC input data, specified as a scalar.

x indicates the number of dacxData ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to Real.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Real part of DAC input, specified as a scalar.

x indicates the number of dacxIData ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxIData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Imaginary part of DAC input, specified as a scalar.

x indicates the number of dacxQData ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxQData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Indication of valid DAC input data, specified as a scalar.

A value of 1 indicates when the data on the dacxData port is valid or when the data on the dacxIData and dacxQData ports is valid.

x indicates the number of dacxValid ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxValid ports.

Data Types: Boolean

Output

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DAC output data, returned as a column vector.

  • If you set the Digital interface parameter to Real, the block returns outputs as a N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    For example, consider N equal to 2 and input to the dac1Data port is of size 32 bits. In this case, this port returns a vector [S0 S1], where S0 is a16-bit value sliced from 0 to 15 bits of input data on the dac1Data port and S1 is a 16-bit value sliced from 16 to 31 bits of input data on the dac1Data port.

  • If you set the Digital interface parameter to I/Q, the block returns outputs as a 2N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

    For example, consider N equal to 2 and inputs to dac1IData and dac1QData ports are of size 32 bits. In this case, this port returns a vector [I0 Q0 I1 Q1], where I0 is a16-bit value sliced from 0 to 15 bits of input data on the dac1IData port and I1 is a 16-bit value sliced from 16 to 31 bits of input data on the dac1IData port and Q0 is a16-bit value sliced from 0 to 15 bits of input data on the dac1QData port and Q1 is a 16-bit value sliced from 16 to 31 bits of input data on the dac1QData port.

x indicates the number of dacx ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacx ports.

Data Types: int16

ADC output data, returned as a scalar.

x indicates the number of adcxData ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to Real.

Data Types: uint16 | uint32 | uint64 | fixed point

Real part of ADC output, returned as a scalar.

x indicates the number of adcxIData ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxIData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: uint16 | uint32 | uint64 | fixed point

Imaginary part of ADC output, returned as a scalar.

x indicates the number of adcxQdata ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxQdata ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: uint16 | uint32 | uint64 | fixed point

Indication of valid ADC output data, returned as a scalar.

A value of 1 indicates that the data on the adcxData port is valid or that the data on the adcxIData and adcxQData ports is valid.

x indicates the number of adcxValid ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface sets the number of adcxValid ports.

Data Types: Boolean

Parameters

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This parameter is read-only.

For details about how to choose a hardware board and configure its parameters, see Hardware Implementation Pane.

Specify the RF channel interface type.

To select a predefined set of ADC and DAC combinations, set this parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, ADC & DAC 8x8 RF Interface, or ADC & DAC 16x16 RF Interface. Available options for this parameter vary as per the selected hardware board. To select the required number of DAC or ADC combinations, set this parameter to Customize.

Example: ADC & DAC 2x2 RF Interface specifies two ADC and two DAC RF channel interfaces.

Specify the digital interface type.

  • Real – Supports real data

  • I/Q – Supports complex data by using real and imaginary ports

Select this parameter to enable multitile synchronization (MTS).

In generation, the Xilinx RF Data Converter tool provides synchronization clocks and ADC and DAC clocks to the RF Data Converter hardware IP. In MTS mode, these synchronization clocks depend on the ADC and DAC sampling rates. Because, the Xilinx RF Data Converter tool provides a set of fixed default synchronization clocks in MTS mode and supports only these sample rates: 737.28, 1474.56, 1966.08, 2457.6, 2949.12, 3072, 3932.16, 4669.44, 4915.2, 5898.24, and 6144.

For more information on MTS mode, see the Xilinx Documentation PDF.

Select this parameter to enable the external phase-locked loop (PLL).

Each ADC and DAC tile includes an internal PLL. This internal PLL together with a clocking instance provides ADC and DAC clocks for each tile as per the ADC or DAC sampling rates. When you select this parameter, the internal PLL disables, and the clocking circuit directly provides ADC and DAC clocks for each tile. The Xilinx RF Data Converter tool supports only these external PLL clock frequencies: 737.28, 1474.56, 1966.08, 2048, 2457.6, 2949.12, 3072, 3194.88, 3276.8, 3686.4, 3932.16, 4096, 4423.68, 4669.44, 4915.2, 5734.4, 5898.24, 6144, 6389.76, 6400, and 6553.6.

DAC

The number of panes and number of DACs in each pane in the DAC tab depend on the selected hardware board. For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, the DAC tab contains two panes (Tile1 and Tile2), and each pane contains four DACs. The tiles and DACs shown on the block mask indicate the corresponding tiles and DACs on the selected hardware board.

The selection of tiles and the respective DACs is predefined when you set the RF interface parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, ADC & DAC 8x8 RF Interface, or ADC & DAC 16x16 RF Interface. You cannot modify the tile and DAC selection when you select these predefined options. To modify the tile and DAC selections, set the RF interface parameter to Customize.

Select this parameter to apply the same parameter values to all of the selected DACs.

Clear this parameter to specify different parameter values for each of the selected DACs.

Dependencies

To enable this parameter, set the RF interface parameter to Customize.

Specify the sample rate as a scalar in a range that is based on the selected hardware board. Units are in mega samples per second.

For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, the sample rate must be in the range [500, 6554].

Specify the interpolation factor.

Note

Gen 1 and Gen 2 devices support interpolation factors of 1, 2, 4, and 8. Gen 3 devices support interpolation factors of 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, and 40.

Specify the number of samples per clock cycle.

The block calculates the stream data width as 16 x Samples per clock cycle.

The block calculates the stream clock frequency as Sample rate (MSPS) / Interpolation mode (xN) x Samples per clock cycle.

Specify the mixer type.

To use Bypassed, set the Digital interface parameter to Real.

To select either Coarse or Fine, set the Digital interface parameter to I/Q.

This parameter is read-only.

To use Real->Real, set the Digital interface parameter to Real.

To use I/Q->Real, set the Digital interface parameter to I/Q.

Specify the mixer frequency.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Coarse.

Specify the numerically controlled oscillator (NCO) frequency values as an m-element row vector, where m is the number of DACs.

When you set the RF interface parameter to Customize and clear the Match parameters of all DACs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter to Fine.

Specify the NCO phase as an m-element row vector, where m is the number of DACs.

When you set the RF interface parameter to Customize and clear the Match parameters of all DACs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter to Fine.

Select this parameter to convert the analog sinc output response from the DAC to a flat-output response.

ADC

The number of panes and number of ADCs in each pane in the ADC tab depend on the selected hardware board. For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, the ADC tab contains four panes (Tile1, Tile2, Tile3, and Tile4), and each pane contains two ADCs. The tiles and ADCs shown on the block mask indicate the corresponding tiles and ADCs on the selected hardware board.

The selection of tiles and the respective ADCs is predefined when you set the RF interface parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, ADC & DAC 8x8 RF Interface, or ADC & DAC 16x16 RF Interface. You cannot modify the tile and ADC selection when you select these predefined options. To modify the tile and ADC selections, set the RF interface parameter to Customize.

Select this parameter to apply the same parameter values to all of the selected ADCs.

Clear this parameter to specify different parameter values for each of the selected ADCs.

Dependencies

To enable this parameter, set the RF interface parameter to Customize.

Specify the sample rate as a scalar in a range that is based on the selected hardware board. Units are in mega samples per second.

For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, the sample rate must be in the range [1000, 4096].

Specify the decimation factor.

Note

Gen 1 and Gen 2 devices support decimation factors of 1, 2, 4, and 8. Gen 3 devices support decimation factors of 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, and 40.

Specify the number of samples per clock cycle.

The block calculates the stream data width as: 16 x Samples per clock cycle.

The block calculates the stream clock frequency as: Sample rate (MSPS) / Decimation mode (xN) x Samples per clock cycle.

Specify the mixer type.

To use Bypassed, set the Digital interface parameter to Real.

To select either Coarse or Fine, set the Digital interface parameter to I/Q.

This parameter is read-only.

To use Real->Real, set the Digital interface parameter to Real.

To use Real->I/Q, set the Digital interface parameter to I/Q.

Specify the mixer frequency.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Coarse.

Specify the numerically controlled oscillator (NCO) frequency values as an m-element row vector, where m is the number of ADCs.

When you set the RF interface parameter to Customize and clear the Match parameters of all ADCs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Fine.

Specify the NCO phase as an m-element row vector, where m is the number of ADCs.

When you set the RF interface parameter to Customize and clear the Match parameters of all ADCs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Fine.

Model Examples

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design

Design a data path for a Xilinx® RFSoC device by using SoC Blockset®. You will design and simulate a system that generates a sinusoidal tone from an FPGA and transmit the tone across multiple RF channels by using the RF Data Converter (RFDC) block. The system will then receive the data back into the FPGA by using the RFDC block and visualizes the received tone for one channel at a time by using an embedded processor.

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 2 Deployment

Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 2 Deployment

Implement and verify a design on Xilinx® RFSoC device using SoC Blockset®. You will deploy a system on Xilinx RFSoC Evaluation kits that generates a sinusoidal tone from an FPGA, transmits it across multiple RF channels and receives it back into the device to complete the loopback. For modeling and simulation of the system, see the Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design example.

5G NR MIB Recovery Using Xilinx RFSoC Device

5G NR MIB Recovery Using Xilinx RFSoC Device

Simulate and deploy a 5G NR MIB Recovery algorithm in Simulink® using an SoC Blockset® implementation targeted on the Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can recover, demodulate a primary synchronization signal (PSS) and secondary synchronization signal (SSS) and decodes MIB report from the 5G NR waveforms and simulate the Cell Search control algorithm sequence running on a processor while interacting with the Cell Search hardware algorithm. In simulation, you can fine tune and verify the controller in the processor and hardware algorithm in the FPGA at a system level before implementing them on the hardware.

OFDM Transmit and Receive Using Xilinx RFSoC Device

OFDM Transmit and Receive Using Xilinx RFSoC Device

Simulate and deploy an orthogonal frequency division multiplexing (OFDM) transmit and receive algorithm in Simulink® using an SoC Blockset® implementation targeted on a Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can integrate HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples into the SoC Blockset implementation.

More About

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Compatibility Considerations

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Behavior changed in R2020b

Extended Capabilities

See Also

External Websites

Introduced in R2020a

SoC Blockset Support Package for Xilinx Devices Documentation

Support