Model External Memory Interfaces

Include external memory interfaces in pixel-streaming designs

You can model and deploy two kinds of external memory interfaces.

External frame buffer interface –– The frame buffer stores a single frame and returns the frame when requested. The interface recreates the streaming video control signals on the output frame. The reference design implements the frame buffer interface using AXI Video DMA.

AXI Master — The AXI Master interface provides read and write access to any address.

Topics

Model Frame Buffer Interface

Add external frame buffer to a pixel-streaming design.

Model AXI Master Interface

Add random-access memory interface to a pixel-streaming design.

Featured Examples

Histogram Equalization with Zynq-Based Hardware

Histogram Equalization with Zynq-Based Hardware

Target a histogram equalization algorithm to the Zynq® hardware using the Vision HDL Toolbox™ Support Package for Xilinx® Zynq-Based Hardware.

Open Model
Image Rotation with Zynq-Based Hardware

Image Rotation with Zynq-Based Hardware

Target an image rotation algorithm to the Zynq® hardware using the Vision HDL Toolbox™ Support Package for Xilinx® Zynq-Based Hardware.

Open Model
Lane Detection with Zynq-Based Hardware

Lane Detection with Zynq-Based Hardware

Target a lane detection algorithm to the Zynq board using the Vision HDL Toolbox™ Support Package for Xilinx® Zynq-Based Hardware. The inverse perspective mapping and lane-marking candidate extraction are targeted to the FPGA, and the ARM processor performs lane-fitting and overlay.

Open Model
Pothole Detection with Zynq-Based Hardware

Pothole Detection with Zynq-Based Hardware

Target a pothole detection algorithm to the Zynq® hardware using the Vision HDL Toolbox™ Support Package for Xilinx® Zynq-Based Hardware.

Open Model

Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware Documentation

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