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Early-Late Gate Timing Recovery

(Removed) Recover symbol timing phase using early-late gate method

Early-Late Gate Timing Recovery has been removed. Use the Symbol Synchronizer block instead.


Timing Phase Recovery sublibrary of Synchronization


The Early-Late Gate Timing Recovery block recovers the symbol timing phase of the input signal using the early-late gate method. This block implements a non-data-aided feedback method.


By default, the block has one input port. Typically, the input signal is the output of a receive filter that is matched to the transmitting pulse shape.

This block accepts a scalar-valued or column vector input signal. The input uses N samples to represent each symbol, where N > 1 is the Samples per symbol parameter.

  • For a column vector input signal, the block operates in single-rate processing mode. In this mode, the output signal inherits its sample rate from the input signal. The input length must be a multiple of N.

  • For a scalar input signal, the block operates in multirate processing mode. In this mode, the input and output signals have different sample rates. The output sample rate equals N multiplied by the input sample rate.

  • This block accepts input signals of type Double or Single

If you set the Reset parameter to On nonzero input via port, then the block has a second input port, labeled Rst. The Rst input determines when the timing estimation process restarts, and must be a scalar.

  • If the input signal is a scalar value, the sample time of the Rst input equals the symbol period

  • If the input signal is a column vector, the sample time of the Rst input equals the input port sample time

  • This block accepts reset signals of type Double or Boolean


The block has two output ports, labeled Sym and Ph:

  • The Sym output is the result of applying the estimated phase correction to the input signal. This output is the signal value for each symbol, which can be used for decision purposes. The values in the Sym output occur at the symbol rate:

    • For a column vector input signal of length N*R, the Sym output is a column vector of length R having the same sample rate as the input signal.

    • For a scalar input signal, the sample rate of the Sym output equals N multiplied by the input sample rate.

  • The Ph output gives the phase estimate for each symbol in the input.

    The Ph output contains nonnegative real numbers less than N. Noninteger values for the phase estimate correspond to interpolated values that lie between two values of the input signal. The sample time of the Ph output is the same as that of the Sym output.


    If the Ph output is very close to either zero or Samples per symbol, or if the actual timing phase offset in your input signal is very close to zero, then the block's accuracy might be compromised by small amounts of noise or jitter. The block works well when the timing phase offset is significant rather than very close to zero.

  • The output signal inherits its data type from the input signal.


When the input signal is a vector, this block incurs a delay of two symbols. When the input signal is a scalar, this block incurs a delay of three symbols.


Samples per symbol

The number of samples, N, that represent each symbol in the input signal. This must be greater than 1.

Error update gain

A positive real number representing the step size that the block uses for updating successive phase estimates. Typically, this number is less than 1/N, which corresponds to a slowly varying phase.

This parameter is tunable in normal mode, Accelerator mode and Rapid Accelerator mode. If you use the Simulink® Coder™ rapid simulation (RSIM) target to build an RSIM executable, then you can tune the parameter without recompiling the model. For more information, see Tunable Parameters (Simulink) in the Simulink User's Guide.


Determines whether and under what circumstances the block restarts the phase estimation process. Choices are None, Every frame, and On nonzero input via port. The last option causes the block to have a second input port, labeled Rst.


This block uses a timing error detector whose result for the kth symbol is e(k), given by



  • yI and yQ are the in-phase and quadrature components, respectively, of the block's input signal

  • T is the symbol period

  • dk is the phase estimate for the kth symbol


[1] Mengali, Umberto and Aldo N. D'Andrea, Synchronization Techniques for Digital Receivers, New York, Plenum Press, 1997.

[2] Sklar, Bernard. Digital Communications: Fundamentals and Applications. Englewood Cliffs, N.J., Prentice-Hall, 1988.

Introduced before R2006a