Discrete FIR Filter HDL Optimized

Finite impulse response filter—optimized for HDL code generation

  • Library:
  • DSP System Toolbox HDL Support / Filtering

Description

The Discrete FIR Filter HDL Optimized block models finite-impulse response filter architectures optimized for HDL code generation. The block accepts one input sample at a time, and provides an option for programmable coefficients. It provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the block models architectural latency including pipeline registers and resource sharing.

The block provides three filter structures. The direct form systolic architecture provides a fully parallel implementation that makes efficient use of Intel® and Xilinx® DSP blocks. The direct form transposed architecture is a fully parallel implementation and is suitable for FPGA and ASIC applications. The partly serial systolic architecture provides a configurable serial implementation that makes efficient use of FPGA DSP blocks. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.

All three structures optimize hardware resources by sharing multipliers for symmetric or antisymmetric filters. The parallel implementations also remove the multipliers for zero-valued coefficients such as in half-band filters and Hilbert transforms.

The latency between valid input data and the corresponding valid output data depends on the filter structure, serialization options, the number of coefficients, and whether the coefficient values provide optimization opportunities. For details of structure and latency, see the Algorithm section.

For a FIR filter with multichannel or frame-based inputs, use the Discrete FIR Filter block instead of this block.

Ports

Input

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Input data, specified as a real or complex scalar. When the input data type is an integer type or a fixed-point type, the block uses fixed-point arithmetic for internal calculations. double and single data types are accepted for simulation but not for HDL code generation.

Data Types: fixed point | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

When valid is true, the block captures the data from the data input port.

Data Types: Boolean

Filter coefficients, specified as a vector of real or complex values. You can change the input coefficients at any time. The size of the vector depends on the size and symmetry of the sample coefficients specified in the Coefficients prototype parameter. The prototype specifies a sample coefficient vector that is representative of the symmetry and zero-value locations of the expected input coefficients. The block uses the prototype to optimize the filter by sharing multipliers for symmetric or antisymmetric coefficients, and removing multipliers for zero-value coefficients. Therefore, provide only the nonduplicate coefficients at the port. For example, if you set the Coefficients prototype parameter to a symmetric 14-tap filter, the block expects a vector of 7 values on the coeff input port. You must still provide zeros in the input coeff vector for the nonduplicate zero-value coefficients.

double and single data types are accepted for simulation but not for HDL code generation.

Dependencies

To enable this port, set Coefficients source to Input port (Parallel interface).

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | fixed point

When reset is true, the block stops the current calculation and clears the internal state of the filter. The reset signal is synchronous and clears the data path and control path states. For more reset considerations, see Tips.

Dependencies

To enable this port, on the Control Ports tab, select Enable reset input port.

Data Types: Boolean

Output

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Filtered output data, returned as a real or complex scalar. When the input data type is a floating-point type, the output data inherits the data type of the input data. When the input data type is an integer type or a fixed-point type, the Output parameter on the Data Types tab controls the output data type.

Data Types: fixed point | single | double
Complex Number Support: Yes

The block sets valid to true with each valid data returned on the data output port.

Data Types: Boolean

The block sets ready to true to indicate that it is ready for new input data on the next cycle.

When using the partly-serial architecture, the block processes one sample at a time. If your design waits for ready to output 0 before de-asserting the input valid, then one extra data input value arrives at the port. The block stores this extra data while processing the current data, and then does not set ready to 1 until the extra input is processed.

Dependencies

Tho enable this port, set Filter structure to Partly serial systolic.

Data Types: Boolean

Parameters

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Main

You can enter constant filter coefficients as a parameter or provide time-varying filter coefficients using an input port.

Selecting Input port (Parallel interface) enables the coeff port on the block and the Coefficients prototype parameter. Specify a prototype to enable the block to optimize the filter implementation according to the symmetry of your coefficients. To use Input port (Parallel interface), set the Filter structure parameter to Direct form systolic.

Discrete FIR filter coefficients, specified as a vector of real or complex values. You can also specify the vector as a workspace variable or as a call to a filter design function. When the input data type is a floating-point type, the block casts the coefficients to the same data type as the input. When the input data type is an integer type or a fixed-point type, you can set the Coefficients data type on the Data Types tab.

Example: firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0])

Dependencies

To enable this parameter, set Coefficients source to Property.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

Prototype filter coefficients, specified as a vector of real or complex values. The prototype specifies a sample coefficient vector that is representative of the symmetry and zero-value locations of the expected input coefficients. If all of your input coefficient vectors have the same symmetry and zero-value coefficient locations, set Coefficients prototype to one of those vectors. If your coefficients are unknown or not expected to share symmetry or zero-value locations, set Coefficients prototype to []. The block uses the prototype to optimize the filter by sharing multipliers for symmetric or antisymmetric coefficients, and removing multipliers for zero-value coefficients.

Coefficient optimizations affect the expected size of the vector on the coeff port. Provide only the nonduplicate coefficients at the port. For example, if you set the Coefficients prototype parameter to a symmetric 14-tap filter, the block shares one multiplier between each pair of duplicate coefficients, so the block expects a vector of 7 values on the coeff port. You must still provide zeros in the input coeff vector for the nonduplicate zero-value coefficients.

Dependencies

To enable this parameter, set Coefficients source to Input port (Parallel interface).

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

HDL filter architecture, specified as one of these structures:

  • Direct form systolic — This architecture provides a fully parallel filter implementation that makes efficient use of Intel and Xilinx DSP blocks. For architecture and performance details, see Fully Parallel Systolic Architecture.

  • Direct form transposed — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For architecture and performance details, see Fully Parallel Transposed Architecture.

  • Partly serial systolic — This architecture provides a serial filter implementation and options for tradeoffs between throughput and resource utilization. It makes efficient use of Intel and Xilinx DSP blocks. The block implements a serial L-coefficient filter with M multipliers and requires input samples that are at least N cycles apart, such that L = N×M. You can specify either M or N. For this implementation, the block provides an output port, ready, that indicates when the block is ready for new input data. For architecture and performance details, see Partly Serial Systolic Architecture (1 < N < L) and Fully Serial Systolic Architecture (N ≥ L).

All implementations share multipliers for symmetric and antisymmetric coefficients. The Direct form systolic and Direct form transposed structures also remove multipliers for zero-valued coefficients.

You can specify the rule that the block uses to serialize the filter as either:

  • Minimum number of cycles between valid input samples – Specify a requirement for input data timing using the Number of cycles parameter.

  • Maximum number of multipliers – Specify a requirement for resource usage using the Number of multipliers parameter.

For a filter with L coefficients, the block implements a serial filter with not more than M multipliers and requires input samples that are at least N cycles apart, such that L = N×M. The block applies coefficient optimizations after serialization, so the M or N value of the final filter implementation can be lower than the value that you specified.

Note

For configuration instructions prior to R2019a, see Changes to Serial Filter Parameters.

Dependencies

To enable this parameter, set the Filter structure parameter to Partly serial systolic.

Serialization requirement for input timing, specified as a positive integer. This parameter represents N, the minimum number of cycles between valid input samples. In this case, the block calculates M = L/N. To implement a fully-serial architecture, set Number of cycles greater than the filter length, L, or to Inf.

The block applies coefficient optimizations after serialization, so the M and N values of the final filter can be lower than the value you specified.

Note

For configuration instructions prior to R2019a, see Changes to Serial Filter Parameters.

Dependencies

To enable this parameter, set Filter structure to Partly serial systolic and set Specify serialization factor as to Minimum number of cycles between valid input samples.

Serialization requirement for resource usage, specified as a positive integer. This parameter represents M, the maximum number of multipliers in the filter implementation. In this case, the block calculates N = L/M. If the input data is complex, the block allocates floor(M/2) multipliers for the real part of the filter and floor(M/2) multipliers for the imaginary part of the filter. To implement a fully-serial architecture, set Number of multipliers to 1 for real input, or 2 for complex input.

The block applies coefficient optimizations after serialization, so the M and N values of the final filter can be lower than the value you specified.

Note

For configuration instructions prior to R2019a, see Changes to Serial Filter Parameters.

Dependencies

To enable this parameter, set the Filter structure to Partly serial systolic, and set Specify serialization factor as to Maximum number of multipliers.

Data Types

Rounding mode for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores the Rounding mode parameter. For more details, see Rounding Modes.

Overflow handling for type-casting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores the Saturate on integer overflow parameter. For more details, see Overflow Handling.

The block type-casts the filter coefficients of the discrete FIR filter to this data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the block ignores this parameter.

The recommended data type for this parameter is Inherit: Same word length as input.

The block returns a warning or error if:

  • The coefficients data type does not have enough fractional length to represent the coefficients accurately.

  • The coefficients data type is unsigned while the coefficients include negative values.

You can disable or control the severity of these data type messages from the model Configuration Parameters, by modifying Diagnostics > Type Conversion > Detect precision loss.

Dependencies

To enable this parameter, set Coefficients source to Property.

The block type-casts the output of the discrete FIR filter to this data type. The quantization uses the settings of the Rounding mode and Overflow mode parameters. When the input data type is floating point, the block ignores this parameter.

The block increases the word length for full precision inside each filter tap and casts the final output to the specified type. The maximum final internal data type (WF) depends on the input data type (WI), the coefficient data type (WC), and the number of coefficients (L) and is given by

WF = WI + WC + ceil(log2(L)).

When you specify a fixed set of coefficients, usually the actual full-precision internal word length is smaller than WF because the coefficient values limit the potential growth. When you use programmable coefficients, the block cannot calculate the dynamic range, and the internal data type is always WF.

Control Ports

When you select this parameter, the reset input port appears on the block. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see Tips.

Select Use HDL global reset to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink®. When this parameter is cleared, the generated HDL global reset clears only control path registers. The generated HDL global reset can be synchronous or asynchronous depending on your Configuration Parameters settings (HDL Code Generation > Global Settings > Reset type).

For more reset considerations, see Tips.

Tips

Reset Behavior

  • By default, the Discrete FIR Filter HDL Optimized block connects the generated HDL global reset to only control path registers. The two reset parameters, Enable reset input port and Use HDL global reset, connect a reset signal to the data path registers. Resetting data path registers can reduce synthesis performance because of the additional routing and loading on the reset signal.

  • The Enable reset input port parameter provides a reset port on the block. The reset signal implements a local synchronous reset of the data path registers. For optimal use of FPGA resources, this option does not connect the reset signal to registers targeted to the DSP blocks of the FPGA.

  • The Use HDL global reset parameter connects the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink. The generated HDL global reset can be synchronous or asynchronous depending on your Configuration Parameters settings (HDL Code Generation > Global Settings > Reset type). Depending on your device, using the global reset may move registers out of the DSP blocks and increase resource use.

  • When you select both the Enable reset input port and Use HDL global reset parameters, both the global and local reset signals clear the control and data path registers.

Reset Considerations for Generated Test Benches

  • FPGA-in-the-loop initialization provides a global reset but does not automatically provide a local reset. With the default reset parameters, the data path registers that are not reset can result in FPGA-in-the-loop (FIL) mismatches if you run the FIL model more than once without resetting the board. Either select Use HDL global reset to reset the data path registers automatically or select Enable reset input port and assert the local reset in your model so it becomes part of the Simulink FIL test bench.

  • The generated HDL test bench provides a global reset but does not automatically provide a local reset. With the default reset parameters and the default register reset Configuration Parameters, the generated HDL code includes an initial simulation value for the data path registers. However, if you are concerned about X-propagation in your design, you can set the register initialization Configuration Parameter (HDL Code Generation > Global Settings > Coding style > No-reset register initialization) to Do not initialize. In this case, with the default block reset parameters, the data path registers that are not reset can cause X-propagation on the data path at the start of HDL simulation. Either select Use HDL global reset to reset the data path registers automatically or select Enable reset input port and assert the local reset in your model so it becomes part of the generated HDL test bench.

Algorithms

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The block provides several filter implementations depending on your parameter settings. The filter implementation considers vendor-specific hardware details of the DSP blocks when adding pipeline registers to the architecture. These differences in pipeline register locations help fit the filter design to the DSP blocks on the FPGA.

The architecture diagrams assume a transfer function that has L coefficients (before optimizations are applied).

Filter structureNumber of cycles (N)Architecture and Performance Link
Direct form systolicN/AFully Parallel Systolic Architecture
Direct form transposedN/AFully Parallel Transposed Architecture
Partly serial systolicN < LPartly Serial Systolic Architecture (1 < N < L)
Partly serial systolicNLFully Serial Systolic Architecture (N ≥ L)

Compatibility Considerations

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Behavior changed in R2019a

Extended Capabilities

Introduced in R2017a