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dsp.HDLFIRDecimation

Finite impulse response (FIR) decimation filter—optimized for HDL code generation

Description

The dsp.HDLFIRDecimation System object™ implements a polyphase FIR decimation filter that is optimized for HDL code generation. It provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the object models architectural latency including pipeline registers and resource sharing.

The object accepts scalar or vector input. When you use vector input, the decimation factor must be an integer multiple of the vector size. The object uses a single-rate implementation. The output is scalar and a valid signal indicates which samples are valid after decimation. The waveform shows an input vector of four samples and a decimation factor of eight. The output sample is valid every second cycle.

The object provides two filter structures. The direct form systolic architecture provides a fully parallel implementation that makes efficient use of Intel® and Xilinx® DSP blocks. The direct form transposed architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.

The object implements one filter for each sample in the input vector. The object then shares this filter between the polyphase subfilters by interleaving the subfilter coefficients in time.

To filter and decimate input data with an HDL-optimized algorithm:

  1. Create the dsp.HDLFIRDecimation object and set its properties.

  2. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects?.

Creation

Description

firDecim = dsp.HDLFIRDecimation creates a default HDL-optimized FIR decimation filter System object.

firDecim = dsp.HDLFIRDecimation(dec,num) sets the DecimationFactor property to dec and the Numerator property to num.

firDecim = dsp.HDLFIRDecimator(___,Name,Value) sets properties using one or more name-value pairs in addition to any input argument combination from previous syntaxes. Enclose each property name in quotes. For example, 'FilterStructure','Direct form transposed' specifies the filter architecture as a fully parallel implementation that is suitable for FPGA and ASIC applications.

Properties

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Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

Main

FIR filter coefficients, specified as a real- or complex-valued vector. You can specify the vector as a workspace variable or as a call to a filter design function. When the input data type is a floating-point type, the object casts the coefficients to the same data type as the input. When the input data type is an integer type or a fixed-point type, you can modify the coefficient data type by using the CoefficientsDataType property.

Example: firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0]) defines coefficients using a linear-phase filter design function.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

HDL filter architecture, specified as one of these structures:

  • 'Direct form systolic' — This architecture provides a fully parallel filter implementation that makes efficient use of Intel and Xilinx DSP blocks.

  • 'Direct form transposed' — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications.

Both implementations share resources by interleaving the subfilter coefficients over one filter implementation for each sample in the input vector.

The object implements a polyphase decomposition filter using dsp.HDLFIRFilter System objects. For architecture details, see the Fully Parallel Systolic Architecture and the Fully Parallel Transposed Architecture sections on the Discrete FIR Filter HDL Optimized block reference page.

Decimation factor, specified as integer greater than two. When you use vector input, the decimation factor must be an integer multiple of the vector size.

Data Types

Rounding method for type-casting the output, specified as 'Floor', 'Ceiling', 'Convergent', 'Nearest', 'Round', or 'Zero'. The object uses this property when casting the output to the data type specified by the OutputDataType property. When the input data type is floating point, the object ignores this property. For more details, see Rounding Modes.

Overflow handling for type-casting the output, specified as 'Wrap' or 'Saturate'. The object uses this property when casting the output to the data type specified by the OutputDataType property. When the input data type is floating point, the object ignores this property. For more details, see Overflow Handling.

Data type of filter coefficients, specified as 'Same word length as input' or a numerictype (Fixed-Point Designer) object. To specify a numerictype object, call numerictype(s,w,f), where:

  • s is 1 for signed and 0 for unsigned.

  • w is the word length in bits.

  • f is the number of fractional bits.

The object casts the filter coefficients to the specified data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the object ignores this property.

Data type of the filter output, specified as 'Same word length as input', 'Full precision', or a numerictype (Fixed-Point Designer) object. To specify a numerictype object, call numerictype(s,w,f), where:

  • s is 1 for signed and 0 for unsigned.

  • w is the word length in bits.

  • f is the number of fractional bits.

The object casts the output of the filter to the specified data type. The quantization uses the settings of the RoundingMethod and OverflowAction properties. When the input data type is floating point, the object ignores this property.

The object increases the word length for full precision inside each filter tap and casts the final output to the specified type. The maximum final internal data type (WF) depends on the input data type (WI), the coefficient data type (WC), and the number of coefficients (L) and is given by

WF = WI + WC + ceil(log2(L)).

Because the coefficient values limit the potential growth, usually the actual full-precision internal word length is smaller than WF.

Control Arguments

Option to enable reset input argument, specified as true or false. When you set this property to true, the object expects a value for the reset input argument. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see Tips.

Option to connect data path registers to generated HDL global reset signal, specified as true or false. Set this property to true to connect the generated HDL global reset signal to the data path registers. This property does not change the arguments of the object or modify simulation behavior in MATLAB®. When you set this property to false, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on your HDL code generation settings.

For more reset considerations, see Tips.

Usage

Description

[dataOut,validOut] = firDecim(dataIn,validIn) filters the input data only when validIn is true.

[dataOut,validOut] = firDecim(dataIn,validIn,reset) filters data when reset is false. When reset is true, the object resets the filter registers. The object expects the reset argument only when you set the ResetInputPort property to true. For more reset considerations, see Tips.

Input Arguments

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Input data, specified as a real- or complex-valued scalar or vector. When you use vector input, the decimation factor must be an integer multiple of the vector size. The vector size must be less than or equal to 64.

When the input data type is an integer type or fixed-point type, the object uses fixed-point arithmetic for internal calculations.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fi | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

Validity of the input data, specified as a logical scalar. The dataIn argument is valid only when this argument is 1 (true).

Data Types: logical

Control signal that clears data path state, specified as a logical scalar. When this argument is 1, the object stops the current calculation and clears the internal state of the filter. The reset signal is synchronous and clears the data path and control path states. For more reset considerations, see Tips.

Dependencies

To enable this argument, set the ResetInputPort property to true.

Data Types: logical

Output Arguments

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Filtered output data, returned as a real- or complex-valued scalar. When the input data is floating point, the output data inherits the data type of the input data. When the input data is an integer type or fixed-point type, the OutputDataType property specifies the output data type.

The output valid signal indicates which samples are valid after decimation.

Data Types: fi | single | double
Complex Number Support: Yes

Validity of the output data, returned as a logical scalar. The object sets this argument to 1 (true) with each valid output data in the dataOut argument.

Data Types: logical

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

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getLatencyLatency of FIR decimation filter
stepRun System object algorithm
releaseRelease resources and allow changes to System object property values and input characteristics
resetReset internal states of System object

Tips

Reset Behavior

  • By default, the dsp.HDLFIRFilter object connects the generated HDL global reset to only the control path registers. The two reset properties, ResetInputPort and HDLGlobalReset, connect a reset signal to the data path registers. Because of the additional routing and loading on the reset signal, resetting data path registers can reduce synthesis performance .

  • The ResetInputPort property enables the reset argument of the object. The reset signal implements a local synchronous reset of the data path registers. For optimal use of FPGA resources, this option does not connect the reset signal to registers targeted to the DSP blocks of the FPGA.

  • The HDLGlobalReset property connects the generated HDL global reset signal to the data path registers. This property does not change the arguments of the object or modify simulation behavior in MATLAB. The generated HDL global reset can be synchronous or asynchronous depending on your HDL code generation settings. Depending on your device, using the global reset might move registers out of the DSP blocks and increase resource use.

  • When you set both the ResetInputPort and HDLGlobalReset properties to true, the global and local reset signals clear the control and data path registers.

Algorithms

This System object implements the algorithms described on the FIR Decimation HDL Optimized block reference page.

Note

The output of the dsp.HDLFIRDecimation object does not match the output from the dsp.FIRDecimation object sample-for-sample. This difference is mainly because of the phase that the samples are applied across the subfilters. To match the dsp.FIRDecimation object, apply DecimationFactor – 1 zeroes to the dsp.HDLFIRDecimation object at the start of the data stream.

The dsp.HDLFIRDecimation object also uses slightly different data types for full-precision calculations. The different data types can also introduce differences in output values if the values overflow the internal datatypes.

Introduced in R2020b