DebugDLProcessorByReadingStatusRegistersExample_01.png
DebugDLProcessorByReadingStatusRegistersExample_02.png
DebugDLProcessorByReadingStatusRegistersExample_03.png
DebugDLProcessorByReadingStatusRegistersExample_04.png
DebugDLProcessorByReadingStatusRegistersExample_05.png
DebugDLProcessorByReadingStatusRegistersExample_06.png
DebugDLProcessorByReadingStatusRegistersExample_07.png
DebugDLProcessorByReadingStatusRegistersExample_08.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_01.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_02.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_03.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_04.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_05.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_06.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_07.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_08.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_09.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_10.png
DefineCustomBoardAndReferenceDesignForDLIPCoreWorkflowExample_11.png
DefineCustomLayerForCustomBitstreamGenerationExample_01.png
DefineCustomLayerForCustomBitstreamGenerationExample_02.png
DefineCustomLayerForCustomBitstreamGenerationExample_03.png
DefineCustomLayerForCustomBitstreamGenerationExample_04.png
DetectObjectsUsingYOLOv4tinyNetworkDeployedToFPGAExample_01.png
DetectObjectsUsingYOLOv4tinyNetworkDeployedToFPGAExample_02.png
DetectObjectsUsingYOLOv4tinyNetworkDeployedToFPGAExample_03.png
GenerateCustomBitstreamToMeetCustomNetworkRequirementsExample_01.png
GenerateCustomGenericDeepLearningProcessorIPCoreExample_01.png
GenerateCustomGenericDeepLearningProcessorIPCoreExample_02.png
GenerateOptimizedDLPConfigurationToMeetFPSRequirementsExample_01.png
MATLABDeploymentUtilExample_01.png
RunGRUProjectedNetworkOnIntelFPGAExample_01.png
RunGRUProjectedNetworkOnIntelFPGAExample_02.png
RunGRUProjectedNetworkOnIntelFPGAExample_03.png
RunGRUProjectedNetworkOnIntelFPGAExample_04.png
RunSequenceForecastingUsingAGRULayerOnAnFPGAExample_01.png
RunSequenceForecastingUsingAGRULayerOnAnFPGAExample_02.png
RunSequenceForecastingUsingAGRULayerOnAnFPGAExample_03.png
RunSequenceForecastingUsingAGRULayerOnAnFPGAExample_04.png
RunSequenceForecastingUsingAGRULayerOnAnFPGAExample_05.png
RunSequenceForecastingUsingAGRULayerOnAnFPGAExample_06.png
RunSequenceForecastingUsingAGRULayerOnAnFPGAExample_07.png
SequenceForecastingUsingDeepLearningOnFPGAExample_01.png
SequenceForecastingUsingDeepLearningOnFPGAExample_02.png
SequenceForecastingUsingDeepLearningOnFPGAExample_03.png
SequenceForecastingUsingDeepLearningOnFPGAExample_04.png
SequenceForecastingUsingDeepLearningOnFPGAExample_05.png
SequencetoSequenceRegressionDeepLearningOnFPGAExample_01.png
SequencetoSequenceRegressionDeepLearningOnFPGAExample_02.png
SequencetoSequenceRegressionDeepLearningOnFPGAExample_03.png
UseAXIBasedBRAMIPToRemoveDDRRequirementExample_01.png
UseAXIBasedBRAMIPToRemoveDDRRequirementExample_02.png
UseAXIBasedBRAMIPToRemoveDDRRequirementExample_03.png
dlhdl_camera_arm_terminal.jpg
dlhdl_camera_hdlwa_interfacetable.jpg
dlhdl_camera_hdlwa_refdesign.jpg
dlhdl_camera_hdlwa_targetplatform.jpg
dlhdl_camera_preprocessing_model.jpg
dlhdl_camera_software_model.jpg
dlhdl_camera_top_level_diagram.png
dlhdl_camera_vivado_DUT.png
dlnFileStructure.png
ipcore_generation_report.png
ipcore_integrated_reference_design.png
system_integration_frame_grab.jpg
vivado_live_video_DUT.png
xxdlhdl_camera_arm_terminal.jpg
xxdlhdl_camera_hdlwa_interfacetable.jpg
xxdlhdl_camera_hdlwa_refdesign.jpg
xxdlhdl_camera_hdlwa_targetplatform.jpg
xxdlhdl_camera_preprocessing_model.jpg
xxdlhdl_camera_software_model.jpg
xxdlhdl_camera_top_level_diagram.png
xxdlhdl_camera_vivado_DUT.png
xxipcore_generation_report.png
xxipcore_integrated_reference_design.png
xxsystem_integration_frame_grab.jpg
xxvivado_live_video_DUT.png
xxzcu102_reference_design_overview.png
zcu102_reference_design_overview.png