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Define and Register Custom Board and Reference Design for SoC Workflow

This example shows how to define and register a custom board and reference design in the HDL Coder™ SoC workflow. Using this example, you will be able to register the Digilent® ZYBO Zynq™ development board and a custom reference design in the HDL Workflow Advisor for the SoC workflow.

This example uses a ZYBO Zynq board, but in the same way, you can define and register a custom board or a custom reference design for the Altera SoC platform.

Requirements

  • Xilinx Vivado 2014.2

  • Digilent® ZYBO Zynq™ development board with the accessory kit

  • HDL Coder support package for Xilinx Zynq-7000

  • Embedded Coder support package for Xilinx Zynq-7000

Set up the ZYBO board

1. Understand the features available on the ZYBO board by reading the reference manual.

2. Set up the ZYBO board as shown in the following figure:

3. Ensure that you have properly installed the USB COM port device drivers on your computer.

4. Configure the JP5 programming mode jumper to enable the loading of a Zynq Linux image from a microSD card connected to connector J4.

5. Configure the JP7 power source select jumper to use a wall outlet as the power source.

6. Connect the shared UART/JTAG USB port on the ZYBO board to your computer.

7. Connect the ZYBO board to your computer using an Ethernet cable. The default ZYBO IP address is 192.168.1.110.

8. Download the ZYBO Zynq Linux image, extract the Zip archive and copy the contents to the microSD card. Insert the microSD card in connector J4.

9. Set up the Xilinx Vivado tool path by using the following command:

hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2014.2\bin\vivado.bat');

Use your own Xilinx Vivado installation path when executing the command.

10. Set up the Zynq hardware connection by using the following commands:

h = zynq();
h.setupZynqHardware();

The setupZynqHardware() method connects to the hardware via the COM port and executes the ifconfig command to obtain the IP address of the board.

Create and export a custom reference design using Xilinx Vivado

A reference design captures the complete structure of an SoC design, defining the different components and their interconnections. The HDL Coder SoC workflow generates an IP core that integrates with the reference design, and is then used to program an SoC board. The following figure describes the relationship between a reference design, an HDL IP core and an SoC board.

In this section, we outline the basic steps necessary to create and export a simple reference design using the Xilinx Vivado IP Integrator environment. For more information about the IP Integrator tool, refer to Xilinx documentations.

1. Create an empty Xilinx Vivado RTL project using xc7z010clg400-2 as the default Xilinx part as shown in the following figure:

2. Create an empty block design and add the Zynq7 Processing System IP block. Download the ZYBO Zynq definition file (ZYBO_zynq_def.xml) from Digilent to the project folder. Re-customize the Zynq7 Processing System IP block using the ZYBO Zynq definition file as shown in the following figure:

3. Complete the block design as shown in the following figure:

Notice that the block design does not contain any information about the HDL IP core.

4. Export the completed block design as a Tcl script design_led.tcl as shown in the following figure:

The exported Tcl script (design_led.tcl) and the ZYBO Zynq definition file (ZYBO_zynq_def.xml) constitute the custom reference design. The Tcl script will be used in the HDL Coder SoC workflow to re-create the block design, customize the Zynq7 Processing System using ZYBO_zynq_def.xml and integrate the generated HDL IP core with the block design in a Xilinx Vivado project.

Caution: The exported Tcl script contains the absolute path to the ZYBO Zynq definition file. Make sure to remove any path information in the Tcl script. Modify the following line in the Tcl script as:

set_property -dict [ list CONFIG.PCW_IMPORT_BOARD_PRESET {ZYBO_zynq_def.xml} ] $processing_system7_0

Register the ZYBO board in HDL Workflow Advisor

In this section, we outline the steps necessary to register the ZYBO board in HDL Workflow Advisor.

1. Create a board registration file with the name hdlcoder_board_customization.m and add it to the MATLAB path.

A board registration file contains a list of board plugins. A board plugin is a MATLAB package folder containing a board definition file and all reference design plugins associated with the board.

The following code describes the contents of a board registration file that contains the board plugin ZyboRegistration to register the ZYBO board in HDL Workflow Advisor.

function r = hdlcoder_board_customization
% Board plugin registration file
% 1. Any registration file with this name on MATLAB path will be picked up
% 2. Registration file returns a cell array pointing to the location of
%    the board plugins
% 3. Board plugin must be a package folder accessible from MATLAB path,
%    and contains a board definition file
r = { ...
    'ZyboRegistration.plugin_board', ...
    };
end

2. Create the board definition file.

A board definition file contains information about the SoC board.

The following code describes the contents of the ZYBO board definition file plugin_board.m that resides inside the board plugin ZyboRegistration.

Information about the FPGA I/O pin locations ('FPGAPin') and standards ('IOSTANDARD') is obtained from the ZYBO master constraints file from Digilent.

The property BoardName defines the name of the ZYBO board as ZYBO in HDL Workflow Advisor.

function hB = plugin_board()
% Board definition
% Construct board object
hB = hdlcoder.Board;
hB.BoardName    = 'ZYBO';
% FPGA device information
hB.FPGAVendor   = 'Xilinx';
hB.FPGAFamily   = 'Zynq';
hB.FPGADevice   = 'xc7z010';
hB.FPGAPackage  = 'clg400';
hB.FPGASpeed    = '-2';
% Tool information
hB.SupportedTool = {'Xilinx Vivado'};
% FPGA JTAG chain position
hB.JTAGChainPosition = 2;
%% Add interfaces
% Standard "External Port" interface
hB.addExternalPortInterface( ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS33'});
% Custom board external I/O interface
hB.addExternalIOInterface( ...
  'InterfaceID',    'LEDs General Purpose', ...
  'InterfaceType',  'OUT', ...
  'PortName',       'LEDs', ...
  'PortWidth',      4, ...
  'FPGAPin',        {'M14', 'M15', 'G14', 'D18'}, ...
  'IOPadConstraint', {'IOSTANDARD = LVCMOS33'});
hB.addExternalIOInterface( ...
   'InterfaceID',    'Push Buttons', ...
   'InterfaceType',  'IN', ...
   'PortName',       'PushButtons', ...
   'PortWidth',      4, ...
   'FPGAPin',        {'R18', 'P16', 'V16', 'Y16'}, ...
   'IOPadConstraint', {'IOSTANDARD = LVCMOS33'});

Register the custom reference design in HDL Workflow Advisor

In this section, we outline the steps necessary to register the custom reference design in HDL Workflow Advisor.

1. Create a reference design registration file named hdlcoder_ref_design_customization.m containing a list of reference design plugins associated with an SoC board.

A reference design plugin is a MATLAB package folder containing the reference design definition file and all files associated with the SoC design project. A reference design registration file must also contain the name of the associated board.

The following code describes the contents of a ZYBO reference design registration file containing the reference design plugin ZyboRegistration.Vivado2014_2 associated with the board ZYBO.

function [rd, boardName] = hdlcoder_ref_design_customization
% Reference design plugin registration file
% 1. The registration file with this name inside of a board plugin folder
%    will be picked up
% 2. Any registration file with this name on MATLAB path will also be picked up
% 3. The registration file returns a cell array pointing to the location of
%    the reference design plugins
% 4. The registration file also returns its associated board name
% 5. Reference design plugin must be a package folder accessible from
%    MATLAB path, and contains a reference design definition file
rd = {'ZyboRegistration.Vivado2014_2.plugin_rd', ...
     };
boardName = 'ZYBO';
end

2. Create the reference design definition file.

A reference design definition file defines the interfaces between the custom reference design and the HDL IP core that will be generated by the HDL Coder SoC workflow.

The following code describes the contents of the ZYBO reference design definition file plugin_rd.m associated with the board ZYBO that resides inside the reference design plugin ZyboRegistration.Vivado2014_2. The property ReferenceDesignName defines the name of the reference design as Demo system (Vivado 2014.2) in HDL Workflow Advisor.

function hRD = plugin_rd()
% Reference design definition
% Construct reference design object
hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado');
hRD.ReferenceDesignName = 'Demo system (Vivado 2014.2)';
hRD.BoardName = 'ZYBO';
% Tool information
hRD.SupportedToolVersion = {'2014.2'};
%% Add custom design files
% add custom Vivado design
hRD.addCustomVivadoDesign( ...
    'CustomBlockDesignTcl', 'design_led.tcl');
% add custom files, use relative path
hRD.CustomFiles = {'ZYBO_zynq_def.xml'};
%% Add interfaces
% add clock interface
hRD.addClockInterface( ...
  'ClockConnection',   'clk_wiz_0/clk_out1', ...
  'ResetConnection',   'proc_sys_reset_0/peripheral_aresetn');
% add AXI4 and AXI4-Lite slave interfaces
hRD.addAXI4SlaveInterface( ...
    'InterfaceConnection', 'axi_interconnect_0/M00_AXI', ...
    'BaseAddress',         '0x40010000', ...
    'MasterAddressSpace',  'processing_system7_0/Data');

In addition to the reference design definition file, a reference design plugin must also contain the SoC design project files.

The ZYBO reference design plugin folder ZyboRegistration.Vivado2014_2 must contain the ZYBO Zynq definition file ZYBO_zynq_def.xml and the Tcl script design_led.tcl exported previously from the Xilinx Vivado project . The ZYBO reference design definition file plugin_rd.m identifies the SoC design project files via the following statements:

hRD.addCustomVivadoDesign('CustomBlockDesignTcl', 'design_led.tcl');
hRD.CustomFiles = {'ZYBO_zynq_def.xml'};

In addition to the SoC design project files, plugin_rd.m also defines the interface connections between the custom reference design and the HDL IP core indicated in the following figure via the statements:

hRD.addClockInterface( ...
  'ClockConnection',   'clk_wiz_0/clk_out1', ...
  'ResetConnection',   'proc_sys_reset_0/peripheral_aresetn');
hRD.addAXI4SlaveInterface( ...
    'InterfaceConnection', 'axi_interconnect_0/M00_AXI', ...
    'BaseAddress',         '0x40010000', ...
    'MasterAddressSpace',  'processing_system7_0/Data');

Caution: The 'BaseAddress' of the AXI4 interface must be a valid address in the 'MasterAddressSpace' and should not create any address conflict with other address based peripherals in the custom reference design.

Execute the SoC workflow for the ZYBO board

The preceding sections discussed the steps to define and register the ZYBO board and a custom reference design in the HDL Workflow Advisor for the SoC workflow. In this section, we use the custom board and reference design registration system to generate an HDL IP core that blinks LEDs on the ZYBO board. The files used in the following demonstration are located at,

  • matlab/toolbox/hdlcoder/hdlcoderdemos/customboards/ZYBO

1. Add the ZYBO board registration file to the MATLAB path using the command,

addpath(fullfile(matlabroot,'toolbox','hdlcoder','hdlcoderdemos','customboards','ZYBO'));

2. Open the Simulink model that implements LED blinking using the command,

open_system('hdlcoder_led_blinking_4bit');

3. Launch HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and selecting HDL Code > HDL Workflow Advisor.

In the Set Target > Set Target Device and Synthesis Tool task, select IP Core Generation for the Target workflow. ZYBO now appears in the drop-down list Target Platform.

4. Click Run This Task to complete the Set Target Device and Synthesis Tool task.

5. In the Set Target > Set Target Interface task, the custom reference design Demo system (Vivado 2014.2) now appears against the Reference design field.

6. Follow the Getting Started with Hardware-Software Co-Design Workflow for Xilinx Zynq Platform example to complete the SoC workflow.

7. Now let us examine the Xilinx Vivado project created by the SoC workflow after completing the Create Project task under Embedded System Integration. The following figure shows the block design of the SoC project where we have highlighted the HDL IP Core. It is instructive to compare this block design with the previous block design used to export the custom reference design for a deeper understanding of the relationship between a custom reference design and an HDL IP Core.

8. The LEDs on the ZYBO board will now start blinking. In addition, you will be able to control the LED blink frequency and direction by executing the software interface model on the Zynq ARM processor.

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