Use “rising_edge/falling_edge” style for registers

Specify if generated should code use rising_edge function or falling_edge function

Model Configuration Pane: Global Settings / Coding style

Description

Specify whether generated code uses the VHDL^® rising_edge function or the falling_edge function to detect clock transitions.

Dependencies

This option is enabled when the target language is VHDL.

Settings

off (default) | on

Default: Off

on

Generated code uses either the rising_edge function or the falling_edge function.

For example, this following code generated from a Unit Delay block uses the rising_edge function to detect positive clock transitions:

Unit_Delay1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay1_out1 <= (OTHERS => '0');
    ELSIF rising_edge(clk) THEN
      IF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

off

Generated code uses the 'event syntax.

For example, this code generated from a Unit Delay block uses clk'event AND clk = '1' to detect positive clock transitions:

Unit_Delay1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay1_out1 <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: UseRisingEdge

Type: character vector

Value: 'on' | 'off'

Default: 'off'

Version History

Introduced in R2012a