Use Verilog or SystemVerilog `timescale directives

Use of compiler directives in generated Verilog or SystemVerilog code

Model Configuration Pane: Global Settings / Coding style

Description

Specify use of compiler `timescale directives in generated Verilog or SystemVerilog code.

Dependencies

This option is enabled when the target language (specified by the Language option) is Verilog or SystemVerilog.

Settings

on (default) | off

Default: On

on

Use compiler `timescale directives in generated Verilog or SystemVerilog code.

off

Suppress the use of compiler `timescale directives in generated Verilog or SystemVerilog code.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

The `timescale directive provides a way of specifying different delay values for multiple modules in a Verilog or SystemVerilog file. This setting does not affect the generated test bench.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: UseVerilogTimescale

Type: character vector

Value: 'on' | 'off'

Default: 'on'

Version History

Introduced in R2012a