Clock Enable Settings and Parameters

This page describes configuration parameters in the Clock Settings section of theHDL Code Generation > Global Settings pane of the Configuration Parameters dialog box. Using these parameters, you can specify the name of the clock enable input port and for internal clock enable signals in the generated code.

Clock enable input port

Specify the name for the clock enable input port in generated HDL code.

Settings

Default: clk_enable

Enter the clock enable input port name in generated HDL code as a character vector.

For example, if you specify 'filter_clock_enable' for the generating subsystem filter_subsys, the generated entity declaration might look as follows:

ENTITY filter_subsys IS
   PORT( clk                 :  IN  std_logic;
         filter_clock_enable :  IN  std_logic;
         reset               :  IN  std_logic;
         filter_subsys_in    :  IN  std_logic_vector (15 DOWNTO 0);
         filter_subsys_out   :  OUT std_logic_vector (15 DOWNTO 0);
         );
END filter_subsys;

The clock enable input signal is asserted active-high (1). Thus, the input value must be high for the generated entity's registers to be updated.

If you specify a VHDL^®, Verilog^® or SystemVerilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL, Verilog or SystemVerilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.

Command-Line Information

Property: ClockEnableInputPort

Type: character vector

Value: A valid identifier in the target language

Default: 'clk_enable'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'ClockEnableInputPort','clken')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockEnableInputPort','clken')
makehdl('sfir_fixed/symmetric_fir')
```

Enable prefix

Specify the base name as a character vector for internal clock enables and other flow control signals in generated code.

Settings

Default: 'enb'

Where only a single clock enable is generated, Enable prefix specifies the signal name for the internal clock enable signal.

In some cases, the code generator can generate multiple clock enable signals. For example, if you specify a cascade block implementation for certain blocks, multiple clock enable signals are generated. In such cases, Enable prefix specifies a base signal name for the first clock enable that is generated. For other clock enable signals, numeric tags are appended to Enable prefix to form unique signal names. For example, the following code fragment illustrates two clock enables that were generated when Enable prefix was set to 'test_clk_enable':

COMPONENT mysys_tc
    PORT( clk                   :   IN    std_logic;
          reset                 :   IN    std_logic;
          clk_enable            :   IN    std_logic;
          test_clk_enable       :   OUT   std_logic;
          test_clk_enable_5_1_0 :   OUT   std_logic
          );
  END COMPONENT;

Command-Line Information

Property: EnablePrefix

Type: character vector

Default: 'enb'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'EnablePrefix','int_enable')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','EnablePrefix','int_enable')
makehdl('sfir_fixed/symmetric_fir')
```