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HDL Code Generation Options in Configuration Parameters Dialog Box

The following figure shows the top-level HDL Code Generation pane in the Configuration Parameters dialog box. To open this dialog box, in the Apps gallery, click HDL Coder. The HDL Code tab appears. In the Prepare section, click Settings.

The HDL Code Generation pane consists of basic options that specify the DUT that you want to generate code for, target language, and folder settings. The Generate HDL for setting is synchronized with the Code for menu in the HDL Code tab. You can also use the buttons in this pane to initiate code generation and perform compatibility checking. The HDL Code Generation pane consists of various subpanes.

To learn more about the parameters in this pane, see Target Language and Folder Selection Parameters.

HDL Code Generation Pane: Target

The HDL Code Generation > Target pane consists of parameters that you can use to specify the target device and synthesis tool. You can also specify the target frequency value in MHz.

To learn more about the parameters in this pane, see Tool and Device Parameters and Target Frequency Parameter.

HDL Code Generation Pane: Optimization

The HDL Code Generation > Optimization pane consists of parameters that you can use to specify various area and speed optimizations to optimize your design. You can also specify use of multicycle path constraints as timing requirement for synthesis tools to meet.

To learn more about the parameters in this pane, see:

HDL Code Generation Pane: Floating Point

The HDL Code Generation > Floating Point pane consists of parameters that you can use to specify the floating-point IP library and additional options depending on whether to use native floating-point support and map to target floating-point IP libraries.

To learn more about the parameters in this pane, see:

HDL Code Generation Pane: Global Settings

The HDL Code Generation > Floating Point pane consists of parameters that you can use to specify the floating-point IP library and additional options depending on whether to use native floating-point support and map to target floating-point IP libraries.

To learn more about the top-level parameters in the Clock Settings section of this pane, see:

The preceding sections contain links to learn more about the parameters in various tabs of this pane.

General Tab

Ports Tab

Coding Style Tab

Coding Standards Tab

Comments Tab

Model Generation and Advanced Tabs

HDL Code Generation Pane: Report

The HDL Code Generation > Report pane consists of parameters that you can use to specify generation of a Code Generation Report with the HDL code. In addition to the summary and clock information, you can specify whether the Code Generation Report report should include sections that display high-level resource utilization, traceability information, effect of various optimizations, and floating-point resource consumption.

To learn more about the parameters in this pane, see Code Generation Report Parameters.

HDL Code Generation Pane: Testbench

The HDL Code Generation > Testbench pane consists of parameters that you can use to specify generation of a testbench to verify the HDL code. You can also specify various testbench options related to clock and reset input signals, setup and hold time, and testbench tolerance parameters.

To learn more about the parameters in this pane, see:

HDL Code Generation Pane: EDA Tool Scripts

The HDL Code Generation > EDA Tool Scripts pane consists of parameters that you can use to specify options that control generation of script files for third-party HDL simulation and synthesis tools.

To learn more about the parameters in this pane, see:

See Also

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