Input and Output Port and Clock Enable Output Type Parameters

This page describes parameters that reside in the HDL Code Generation > Global Settings > Ports tab of the Configuration Parameters dialog box.

Input data type

Specify the HDL data type for the input ports of the model.

Settings

For VHDL^®, the options are:

Default: std_logic_vector

std_logic_vector: Specifies VHDL type STD_LOGIC_VECTOR.
signed/unsigned: Specifies VHDL type SIGNED or UNSIGNED.

For Verilog^® and SystemVerilog, the options are:

Default: wire

In generated Verilog and SystemVerilog code, the data type for all ports is 'wire', and cannot be modified. Therefore, Input data type is disabled when the target language is Verilog or SystemVerilog.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

Property: InputType

Type: character vector

Value: (for VHDL)'std_logic_vector' | 'signed/unsigned'

(for Verilog) 'wire'

Default: (for VHDL) 'std_logic_vector'

(for Verilog) 'wire'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Output data type

Specify the HDL data type for the output ports of the model.

Settings

For VHDL, the options are:

Default: Same as input data type

Same as input data type: Specifies that output ports of the model have the same type specified by Input data type.
std_logic_vector: Specifies VHDL type STD_LOGIC_VECTOR as the data type of the output port.
signed/unsigned: Specifies VHDL type SIGNED or UNSIGNED as the data type of the output port.

For Verilog and SystemVerilog, the options are:

Default: wire

In generated Verilog and SystemVerilog code, the data type for all ports is 'wire', and cannot be modified. Therefore, Output data type is disabled when the target language is Verilog or SystemVerilog.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

Property: OutputType

Type: character vector

Value: (for VHDL)'std_logic_vector' | 'signed/unsigned'

(for Verilog) 'wire'

Default: If the property is left unspecified, output ports have the same type specified by InputType.

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Clock Enable output port

Specify the name for the generated clock enable output port as a character vector.

Settings

Default: ce_out

A clock enable output is generated when the design requires one.

Command-Line Information

Property: ClockEnableOutputPort

Type: character vector

Default: 'ce_out'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.