Pipelining Parameters

This documentation page describes configuration parameters that reside in the HDL Code Generation > Optimization > Pipelining tab of the Configuration Parameters dialog box. Using the parameters in this section, you can improve the timing of your design on the target device.

Allow design delay distribution

Specify whether to allow distributed pipelining and delay absorption optimizations to move design delays in your model.

Settings

Default: On

On: Allow distributed pipelining and delay absorption to move or absorb design delays in the model.
Off: Prevent distributed pipelining and delay absorption from moving or absorbing design delays in the model.

Command-Line Information

Property: AllowDelayDistribution

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the AllowDelayDistribution setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'AllowDelayDistribution','off')

Use hdlset_param to disable the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','AllowDelayDistribution','off')
makehdl('sfir_fixed/symmetric_fir')
```

Pipeline distribution priority

Specify the priority for the distributed pipelining and delay absorption optimizations.

Settings

Default: Numerical Integrity

Numerical Integrity

Prioritize numerical integrity.

This option uses a conservative retiming algorithm that does not move registers across a component if the functional equivalence to the original design is unknown.

Performance

Prioritize performance over numerical integrity.

Use this option if your design requires a higher clock frequency and the Simulink^® behavior does not need to strictly match the generated code behavior during the initialization cycles. This option uses a more aggressive retiming algorithm that moves registers across a component even if the modified design’s functional equivalence to the original design is unknown. You can also use this option to reduce area by preventing distributed pipelining from inserting pipeline registers on stable paths.

Command-Line Information

Property: PipelineDistributionPriority

Type: character vector

Value: 'Numerical Integrity' | 'Performance'

Default: 'Numerical Integrity'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the PipelineDistributionPriority setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'PipelineDistributionPriority','Performance')

Use hdlset_param to set the parameter on the model and then generate HDL code using makehdl.

hdlset_param('sfir_fixed','PipelineDistributionPriority','Performance')
makehdl('sfir_fixed/symmetric_fir')

Clock-rate pipelining

If your design contains multicycle paths, use clock-rate pipelining to insert pipeline registers at a clock rate that is faster than the data rate. This optimization improves the clock frequency and reduces the area usage without introducing additional latency. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.

Settings

Default: On

On: Insert pipeline registers at the clock rate for multi-cycle paths.
Off: Insert pipeline registers at the data rate for multi-cycle paths.

Dependency

If you specify an Oversampling factor greater than one or select Treat Simulink rates as actual hardware rates, make sure that you select the Clock-rate pipelining check box. Clock-rate pipelining identifies regions in your model that run at the same slow data rate and are delimited by Delay blocks or blocks that introduce a rate transition. The code generator converts these regions to the faster clock rate by introducing Repeat blocks at the input of the region and Rate Transition blocks at the output of the region.

Command-Line Information

Property: ClockRatePipelining

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the ClockRatePipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'ClockRatePipelining','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockRatePipelining','on')
makehdl('sfir_fixed/symmetric_fir')
```

Allow clock-rate pipelining of DUT output ports

Produce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate.

Settings

Default: Off

On: Produce the DUT outputs as soon as possible at the clock rate.
Off: Produce the DUT outputs at the data rate.

Dependency

When you specify this parameter, make sure that you select the Clock-rate pipelining check box.

Command-Line Information

Property: ClockRatePipelineOutputPorts

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the ClockRatePipelineOutputPorts setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'ClockRatePipelineOutputPorts','on')

When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.
```
hdlset_param('sfir_fixed','ClockRatePipelineOutputPorts','on')
makehdl('sfir_fixed/symmetric_fir')
```

Balance clock-rate pipelined DUT output ports

Synchronize the DUT outputs while satisfying the highest-latency requirements of the outputs. Apply this option when interfacing your logic with a valid signal interface to align the output of the logic path and valid signal path.

Settings

Default: Off

On: Synchronize the DUT outputs.
Off: Produce the DUT outputs as soon as possible, without synchronization.

Dependency

To enable this parameter, select the Allow clock-rate pipelining of DUT output ports check box.

Command-Line Information

Property: BalanceClockRateOutputPorts

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the BalanceClockRateOutputPorts setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'BalanceClockRateOutputPorts','on')

When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.
```
hdlset_param('sfir_fixed','BalanceClockRateOutputPorts','on')
makehdl('sfir_fixed/symmetric_fir')
```

Distributed pipelining

Enable pipeline register distribution, which is a speed optimization that increases the clock speed by moving existing delays in a design to reduce the critical path. This optimization moves the delays within a subsystem while preserving the hierarchy. For more information, see Distributed Pipelining.

Settings

Default: Off

On: Distribute pipelines in your design. To distribute pipelines, you must have pipelines already specified in your design.
Off: Do not distribute pipelines in your design.

Dependency

Your design must contain delays that can be redistributed. You can insert delays manually or by using the HDL block properties InputPipeline or OutputPipeline on a subsystem or block.

Command-Line Information

Property: DistributedPipelining

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the DistributedPipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'DistributedPipelining','on')

When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.
```
hdlset_param('sfir_fixed','DistributedPipelining','on')
makehdl('sfir_fixed/symmetric_fir')
```

Use synthesis estimates for distributed pipelining

To determine more accurate propagation delays for each component, use synthesis timing estimates for distributed pipelining. Different weights are assigned to varying components, which more accurately reflects how the components function on hardware. When you enable this parameter, HDL Coder™ can better distribute pipelines in your design for HDL code generation and hardware deployment to maximize the clock frequency for your target device.

Settings

Default: Off

On: Use synthesis timing estimates for calculating propagation delays for each component in your design for distributed pipelining.
Off: Use equal weights for calculating propagation delays for each component in your design for distributed pipelining.

Dependency

Distributed pipelining must be enabled for at least one subsystem in your model to use this parameter.

Command-Line Information

Property: UseSynthesisEstimatesForDistributedPipelining

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can enable the UseSynthesisEstimatesForDistributedPipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'UseSynthesisEstimatesForDistributedPipelining','on')

When you use hdlset_param, set the parameter on the model, and then generate HDL code by using the makehdl function.
```
hdlset_param('sfir_fixed','UseSynthesisEstimatesForDistributedPipelining','on')
makehdl('sfir_fixed/symmetric_fir')
```

Adaptive pipelining

Use this parameter to insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.

Settings

Default: Off

On: Insert adaptive pipeline registers in your design. For HDL Coder to insert adaptive pipelines, you must specify the synthesis tool.
Off: Do not insert adaptive pipeline registers.

Dependency

When you specify this parameter, in the HDL Code Generation > Target pane, specify the Synthesis Tool. If your design has multipliers, specify the Synthesis Tool and the Target Frequency (MHz) for adaptive pipeline insertion.

Command-Line Information

Property: AdaptivePipelining

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the AdaptivePipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
                    'AdaptivePipelining','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','AdaptivePipelining','on')
makehdl('sfir_fixed/symmetric_fir')
```

Map lookup tables to RAM

Use this parameter to map lookup tables in your design to block RAM and reduce area usage on the target FPGA device.

Settings

Default: On

On: Map lookup tables in your design to RAM.
Off: Do not map lookup tables in your design to RAM.

Command-Line Information

Property: LUTMapToRAM

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the LUTMapToRAM setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'LUTMapToRAM','on')

When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.
```
hdlset_param('sfir_fixed','LUTMapToRAM','on')
makehdl('sfir_fixed/symmetric_fir')
```