Manchester Receiver Using Mixed Design (Verilog and VHDL)

This example shows verification of a Manchester encoder using mixed HDL languages, VHDL and Verilog. Manchester encoding is a simple modulation scheme which converts baseband digital data into an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

This model simulates a pure-digital receiver of Manchester encoded data. The receiver is implemented in VHDL/Verilog. The receiver uses a simple DLL clock recovery mechanism, which requires multiple cycles to lock with the incoming data stream. The performance of the receiver is explored by applying phase and frequency errors to a randomly generated stream of bits that is encoded using a simple MATLAB® function: manchesterencoder().

The actual VHDL/Verilog code will run in ModelSim®/Incisive® using the cosimulation block called "Mixed HDL Manchester Receiver"

In this example VHDL implementations are used for the lower level blocks and the top block implementation is in Verilog. Connections are made to some signals in Verilog and others in VHDL via the ports pane of the EDA Simulator Link block. In spite of the differences in HDL languages, the syntax for the connections is consistent. It is also important to notice that the ports pane is used here to connect to HDL signals that are not actually ports at the top-level module. In fact, connections can be made to signals at any level of the HDL hierarchy by the HDL Verifier cosimulation block.

Languages used for the implementations of the HDL blocks:

  • top-level (manchester): Verilog

  • decoder: VHDL

  • iq converter: VHDL

  • state counter: VHDL

The actual VHDL and Verilog code will run in the HDL simulator and its execution will be seen in Simulink as the behavior of the EDA Simulator Link cosimulation block called "Mixed HDL Manchester Receiver."

Open the ModelSim® mixed-language model.

Open the Incisive® mixed-language model.