MATLAB® and Simulink® support Cadence® verification tools using HDL Verifier™. Use one of these recommended versions, which have been fully tested against the current release:
INCISIV 13.2 p002
INCISIV 13.1 s006
INCISIV 12.2 s007
The HDL Verifier shared libraries (
are built using the gcc included in the Cadence Incisive® simulator
platform distribution. Before you link your own applications into
the HDL simulator, first try building against this gcc. See the HDL
simulator documentation for more details about how to build and link
your own applications.
MATLAB and Simulink support Mentor Graphics® verification tools using HDL Verifier. Use one of the following recommended versions. Each version has been fully tested against the current release:
QuestaSim 10.3, 10.2c, 10.2b
ModelSim®/QuestaSim PE 10.2c, 10.1a
ModelSim/QuestaSim DE 10.1a
ModelSim SE 10.1c
The Linux® platform requires that HDL Verifier software run gcc c++ libraries (4.1 or later). You should install a recent version of the gcc c++ library on your computer. To determine which libraries are installed on your computer, type the command:
MATLAB and Simulink support Xilinx® design tools using HDL Verifier.
FPGA-in-the-Loop is tested with Xilinx ISE 14.7 and Xilinx Vivado® 2013.4.
Xilinx ISE is required for FPGA boards in the Spartan-6, Virtex-4, Virtex-5, and Virtex-6 families. For all other supported FPGA families, Xilinx Vivado is required.
ISE 11.1 or newer is recommended
Consult Xilinx user documentation for compatibility of ISE tools with various Linux distributions.
Note: Xilinx does not ship the Digilent® plugin with ISE 14.2. To get the plugin, see the Digilent plugin and related software download page on the Digilent web site.
MATLAB and Simulink support Altera® design tools using HDL Verifier.
FPGA-in-the-Loop is tested with Altera Quartus II 13.1.
|Vendor||Supported Devices||Required Hardware||Required Software|
Any Altera FPGA board within the supported FPGA family, for example:
The FPGA board must be using an FPGA device in the supported Xilinx FPGA family: Virtex 7, Kintex 7 , Artix® 7 and Zynq 7000.
All Xilinx 7-series FPGA boards that HDL Verifier supports directly (as of this release) can perform simulation through an on-board Digilent JTAG cable. Additional boards using the supported FPGA devices can be added with the FPGA Board Manager.
The FPGA board must be using a Digilent download cable. If your board has a standard Xilinx 14 pin JTAG connector, you can obtain the HS2 cable from Digilent.
Gigabit Ethernet card
Cross-over Ethernet cable
FPGA board with supported Ethernet connection
PHY Interface Type:
Gigabit Ethernet — GMII
Gigabit Ethernet — RGMII
Gigabit Ethernet — SGMII
Ethernet — MII
There are no software requirements for an Ethernet connection, but the firewall on the host computer should not prevent UDP communication for FIL
HDL Verifier supports FIL simulation on the devices shown in the following table. The board definition files for these boards are in the Download FPGA Board Support Package. You may also add other FPGA boards for use with FIL with FPGA board customization ().
|Xilinx Spartan-6||Spartan-6 SP605|
XUP Atlys Spartan-6
|Xilinx Virtex-7||Virtex-7 VC707|
|Xilinx Virtex-6||Virtex-6 ML605|
|Xilinx Virtex-5||Virtex-5 ML505|
|Xilinx Virtex-4||Virtex-4 ML401|
|Xilinx Kintex-7||Kintex-7 KC705|
|Altera Arria II||Arria II GX FPGA development kit|
|Altera Arria V||Arria V SoC development kit|
|Altera Cyclone IV||Cyclone IV GX FPGA development kit|
DE2-115 development and education board
|The Altera DE2-115 FPGA development board has two Ethernet ports. FPGA-in-the-loop uses only Ethernet 0 port. Make sure that you connect your host computer with the Ethernet 0 port on the board via an Ethernet cable.|
|Altera Cyclone III||Cyclone III FPGA development kit|
Altera Nios II Embedded Evaluation Kit, Cyclone III Edition
|Altera Cyclone V||Cyclone V FPGA GX development board|
Cyclone V SoC development kit
Cyclone V GT development kit
Arrow SoC development kit
|The Cyclone V SoC and Arrow SoC development kits are supported for JTAG connection only.|
|Altera Stratix IV||Stratix IV GX FPGA development board|
|Altera Stratix V||Stratix V DSP Development Kit|
Ethernet PHY RGMII interface is not supported for Xilinx Spartan6 family when used with FPGA-in-the-loop.
For FPGA development boards that have more than one FPGA device, only one such device can be used with FIL.
FPGA Board Support Packages. The FPGA board support packages contain the definition files for all supported boards. You may download one or more vendor-specific packages, but you must download one of the packages before you can use FIL or customize your own board definition file using the New FPGA Board Wizard (see Create Custom FPGA Board Definition).
Visit the Hardware
Support Catalog for a list of currently supported devices
and boards. Download an FPGA board support package with the
HDL Verifier supports the following FPGA device families for board customization; that is, when you create your own board definition file. See FPGA Board Customization.
With the current release, TLMG includes support for:
Visual Studio®: VS2005, VS2008, VS2010, and VS2012
SystemC 2.3.1 (TLM included)
You can download SystemC and TLM libraries at http://accellera.org. Consult the Accellera Systems Initiative web site for information about how to build these libraries after downloading.