MATLAB® and Simulink® support Cadence® verification tools using HDL Verifier™. Use one of these recommended versions, which have been fully tested against the current release:
Incisive® 13.2 p002
Incisive 13.1 s006
Incisive 12.2 s007
The HDL Verifier shared libraries (
are built using the gcc included in the Cadence Incisive® simulator
platform distribution. Before you link your own applications into
the HDL simulator, first try building against this gcc. See the HDL
simulator documentation for more details about how to build and link
your own applications.
MATLAB and Simulink support Mentor Graphics® verification tools using HDL Verifier. Use one of the following recommended versions. Each version has been fully tested against the current release:
Questa®Sim 10.4c, 10.3, 10.2c
ModelSim®/QuestaSim PE 10.4c, 10.3e, 10.2c
MATLAB and Simulink support Xilinx® design tools using HDL Verifier.
FPGA-in-the-loop is tested with Xilinx ISE 14.7 and Xilinx Vivado® 2015.2.
Xilinx ISE is required for FPGA boards in the Spartan®-6, Virtex®-4, Virtex-5, and Virtex-6 families. For all other supported FPGA families, Xilinx Vivado is required.
ISE 11.1 or newer is recommended
Consult Xilinx user documentation for compatibility of ISE tools with various Linux® distributions.
MATLAB and Simulink support Altera® design tools using HDL Verifier.
FPGA-in-the-loop is tested with Altera Quartus II 15.0.
For board support, see Supported FPGA Devices for FIL Simulation.
Additional boards can be custom added with the FPGA Board Manager. See Supported FPGA Device Families for Board Customization.
|Vendor||Supported Devices||Required Hardware||Required Software|
The FPGA board must be using an FPGA device in the supported Altera FPGA families.
The board must be using one of the following supported Xilinx FPGAs: Artix®-7, Virtex-7, Kintex®-7 or Zynq® 7000.
Note: When simulating your FPGA design through Digilent JTAG cable with Simulink or MATLAB, you can not use any debugging software that requires access to the JTAG; for example,Vivado Logic Analyzer.
|Required Hardware||Supported Interfaces||Required Software|
There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.
Note: FIL over PCI Express® connection is supported only for 64-bit Windows operating systems.
|Device Family||Board||Required Software|
|Altera||Altera Quartus II 15.0|
HDL Verifier supports FIL simulation on the devices shown in the following table. The board definition files for these boards are in the Download FPGA Board Support Package. You can add other FPGA boards for use with FIL with FPGA board customization (FPGA Board Customization).
Xilinx Zynq boards support a JTAG connection only.
Digilent Nexys™4 Artix-7
XUP Atlys Spartan-6
Xilinx Kintex UltraScale™
Kintex UltraScale FPGA KCU105 Evaluation Kit
Altera Arria® II
|Arria II GX FPGA Development Kit|
Altera Arria V
|Arria V SoC Development Kit|
Arria V Dtarter Kit
The Altera Arria V SoC development kit supports a JTAG connection only.
Altera Cyclone IV
|Cyclone IV GX FPGA Development Kit|
DE2-115 Development and Education Board
|The Altera DE2-115 FPGA development board has two Ethernet ports. FPGA-in-the-loop uses only Ethernet 0 port. Make sure that you connect your host computer with the Ethernet 0 port on the board via an Ethernet cable.|
Altera Cyclone III
|Cyclone III FPGA Starter Kit|
Cyclone III FPGA Development Kit
Altera Nios II Embedded Evaluation Kit, Cyclone III Edition
The Altera Cyclone III FPGA starter kit supports a JTAG connection only.
Altera Cyclone V
|Cyclone V GX FPGA Development Kit|
Cyclone V SoC Development Kit
Cyclone V GT Development Kit
Arrow® SoCKit Development Kit
|The Cyclone V SoC and Arrow SoCKit development kits are supported for JTAG connection only.|
Altera Stratix IV
|Stratix IV GX FPGA Development Kit|
Altera Stratix V
|DSP Development Kit, Stratix V Edition|
Altera MAX® 10
Arrow MAX 10 DECA
Ethernet PHY RGMII interface is not supported for Xilinx Spartan6 family when used with FPGA-in-the-loop.
For FPGA development boards that have more than one FPGA device, only one such device can be used with FIL.
FPGA Board Support Packages. The FPGA board support packages contain the definition files for all supported boards. You can download one or more vendor-specific packages. To use FIL, download at least one of these packages, or customize your own board definition file. See Create Custom FPGA Board Definition.
Visit the Hardware
Support Catalog for a list of currently supported devices
and boards. Download an FPGA board support package with the
HDL Verifier supports the following FPGA device families for board customization; that is, when you create your own board definition file. See FPGA Board Customization.
With the current release, TLMG includes support for:
Visual Studio®: VS2008, VS2010, VS2012, and VS2013
Windows 7.1 SDK
SystemC 2.3.1 (TLM included)
You can download SystemC and TLM libraries at http://accellera.org. Consult the Accellera Systems Initiative website for information about how to build these libraries after downloading.
System C Modeling Library (SCML):
You can download SCML from https://www.synopsys.com.